一個僅200nA靜態電流且使用十二奈米鰭式電晶體的 被動漣波導通關斷控制降壓型轉換器

Abstract

這篇論文介紹了一種純NMOS電晶體功率級(power stage)、被動式斜率補償(Passive ramp)、導通-關斷時間控制(on-off-time control)且靜態電流(quiescent current)僅有200 nA的降壓轉換器(buck converter)。在設計中，還有一種被稱為深度睡眠(deep sleep mode)的模式，可以在必要時將除了少數主要比較器與少數偏壓電路之外的整個控制電路群關閉。使用被動式斜率補償也規避了相較於傳統上較為耗電的斜率產生器。這些功能最佳化了此電路的靜態電流，甚至在極低負載中(ultra-light load)有一半以上的功率損耗是來自於製程上無法避免的漏電。在小訊號分析中，由輸出電感與輸出電容產生的複數極點(LC complex pole)會被被動式斜率補償中的前饋(feed forward)機制解耦(decouple)。我們也設計了一個較低頻寬的迴路，用來做直流偏壓消去(DC offset cancellation)。它能夠在不影響暫態響應的同時，決定的整個電路的頻寬與穩定度。這種雙迴路(dual loop)能夠同時保證輸出電壓的穩定與快速的暫態響應。為了達成200 nA靜態電流的目標，我們設計了一個帶隙參考電壓(bandgap reference)，它會在深度睡眠模式時切換到低漏電採樣模式(low leakage sample and hold)，使其可以僅在極短時間內運作，常時保持關閉，使其平均功耗降到極低。在負載暫態響應方面，我們提出了一種創新的導通-關斷時間控制(on-off-time control)的控制法，可以在導通時間控制(on-time control)與關斷時間控制(off-time control)自動且順暢的切換，使得導通時間與關閉時間皆能隨著負載變化而自由延展。 所提之晶片原型採用台積電12nm CMOS製程，並且在包含了功率級與引腳的同時僅僅占用0.36 mm2的面積。純NMOS電晶體功率級與共封裝的去彈跳電路(debouncing circuit)與靴帶式電路(bootstrap circuit)表現出僅有35 mOhm的導通電阻(Rdson)。在模擬中顯示，切換頻率最高為4.8 MHz、僅有200 nA的靜態電流且在負載從10 μA到2 A皆有大於90%的效率。而在1 μA與500mA的負載瞬態響應中，所提出的導通-關斷時間控制達成23 mV/ 17 mV 的過衝/下衝，與800-ns的安定時間。這個降壓轉換器架構最初由蔡杰儒學長提出並由我進行電路設計與實現。

This thesis presents a 200nA quiescent current, pure NMOS power stage, passive ramp (PSR) on-off-time controlled buck converter for a modern mobile silicon-on-chip (SoC) for a longer battery life. In the design, there’s a mode called deep sleep mode (DSM) that only the main comparator is alive in the whole circuit. Passive ramp modulation also plays an important role to prevent the conventional power-hungry ramp generator. These functions extremely improve the quiescent current to a new level. Eventually more than half of the power consume is leakage current. In a small signal analysis scheme, the LC complex poles are decoupled by the feedforward component benefit from PSR modulation. I also design an extra loop with relatively low bandwidth for DC correction. It also defines the bandwidth of the whole loop but not affecting the modulator gain. This dual loop scheme ensures the stable output voltage DC level and the fast transient speed, simultaneously. To achieve 200nA quiescent current, I also design a bandgap reference that can be totally shut down with a low leakage sample and hold technique. For load transient response, an innovative on-off-time control scheme is proposed. The modulation of this control switched between on-time and off-time control, smoothly and automatically. The proposed chip prototype is fabricated in TSMC 12nm CMOS process and only occupies 0.36mm2 with the power stage and pads. An N-FinFET power stage with co-package designed debounce circuitry and bootstrap circuit performs a 35 mOhm Rdson with all trace resistance. It shows a 4.8MHz switching frequency, 200nA quiescent current, and a loading range from 10μA to 2A with > 90% efficiency in simulation. The proposed passive ramp constant-on-off time controller achieves a 23 mV/ 17 mV undershoot/overshoot voltage with 800 ns settling time with a 1 μA to 500 mA loading step. The architecture of the buck converter was initially proposed by Senior Scholar Chieh-Ju Tsai and subsequently, I undertook the circuit design and implementation.