應用於無線通訊與天文接收系統之D頻段與Q頻段CMOS低雜訊放大器設計

Abstract

本論文分為兩部分，分別針對D頻段及Q頻段低雜訊放大器（LNA）之設計與實測，應用於6G無線通訊與天文接收系統。 第一部分提出一款採用65奈米CMOS製程之D頻段LNA，採用三級Gmax-core架構以兼顧高增益與低雜訊。第一級同步進行雜訊與輸入匹配最佳化，並提出改良之電晶體模擬方法，以提升高頻模擬與量測結果一致性。量測結果顯示，電路於140 GHz具22 dB峰值增益、8.2 dB最低雜訊指數，於130–145 GHz頻帶內維持逾15 dB增益，直流功耗僅17.3 mW，驗證CMOS技術於6G高頻前端應用之可行性。 第二部分則提出一款以90奈米CMOS製程實現之Q頻段LNA。電路首級採用變壓器耦合共源共閘架構以抑制後級雜訊，並於次級導入電流再利用技術提升增益與功率效率。量測結果顯示，該LNA於46.6 GHz具15.7 dB最大增益，3 dB頻寬覆蓋36.6–46.6 GHz，最低及平均雜訊指數分別為3.3 dB與3.8 dB，總直流功耗僅7.8 mW，展現優異性能及良好權衡。

This thesis presents the design and measurement of low-noise amplifiers (LNAs) in the D-band and Q-band, targeting next-generation wireless communication systems and radio astronomy receivers. The first part describes a D-band LNA fabricated using a 65-nm CMOS process, employing a three-stage Gmax-core architecture to achieve high gain and low noise. The first stage is optimized for noise and input matching, while an improved transistor modeling approach is introduced to enhance the agreement between simulation and measurement at high frequencies. The LNA demonstrates a peak gain of 22 dB at 140 GHz, a minimum noise figure of 8.2 dB, and maintains over 15 dB gain from 130 to 145 GHz. With a power consumption of 17.3 mW, the results confirm the feasibility of CMOS technology for high-frequency 6G front-end circuits. The second part presents a Q-band LNA implemented in a 90-nm CMOS process. A transformer-coupled cascode is used in the first stage to suppress noise from subsequent stages, and a current-reuse technique is adopted in the second stage to boost gain with limited power. Measurement results show a maximum gain of 15.7 dB at 46.6 GHz and a 3-dB bandwidth of 36.6–46.6 GHz. The minimum and average noise figures are 3.3 dB and 3.8 dB, respectively. Total DC power consumption is only 7.8 mW, demonstrating an effective trade-off between gain, noise figure, and power efficiency.