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  1. NTU Theses and Dissertations Repository
  2. 電機資訊學院
  3. 電機工程學系
Please use this identifier to cite or link to this item: http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/96431
Title: 應用於電源管理積體電路的先進控制及電路技巧
Advanced Control and Circuit Technique for Power Management IC
Authors: 蔡杰儒
Chieh-Ju Tsai
Advisor: 陳景然
Ching-Jan Chen
Keyword: 電源管理積體電路,多相降壓轉換器,電流感測,相位交錯,自適應導通時間V2控制,低靜態電流,快速瞬態響應,
Power management integrated circuits (PMICs),multiphase buck converter,current sensing,phase interleaving,adaptive on-time V2 control,low Iq,fast transient,
Publication Year : 2025
Degree: 博士
Abstract: 本論文詳細介紹了針對系統單晶片 (SoC) 應用的三種創新電源管理積體電路 (PMIC) 設計:

行動遊戲應用:
本研究提出了多相降壓轉換器中電流平衡和相位交錯的創新技術。我們開發了一款雙相降壓轉換器,採用自減式 RLG 電流感測器,實現了緊湊的設計,同時顯著提升了電流共享的準確性和感測誤差。該轉換器使用台積電 0.18 μm CMOS 製程製造,晶片總面積為 0.586 mm²,其中電流感測器部分佔 0.062 mm²。設計達到了 1 A 至 2 A 負載範圍內的電流平衡誤差小於 2.2%,相間電流共享準確性提升 71%,且在 1.2 A 至 2.6 A 的負載範圍內感測誤差小於 50 mA。
此外,透過引入使用自適應導通時間控制的相位插值器,提高了系統的動態性能和抗噪能力。每相運行頻率為 3 MHz,最大抖動為 30.25 ns,且在波紋消除點的相位誤差為 7.3 度。該原型同樣採用台積電 0.18 μm 製程,佔用 1.41 mm² 的面積(其中相位插值器部分為 0.03 mm²),達到 95.58% 的峰值效率,並在 3 A 負載步階下,電壓下跌 80 mV,回復時間為 2 μs。

AIoT 應用:
我們提出了一款具有超低靜態電流 (55 nA) 的降壓轉換器,採用 AOT V2 拓撲。該轉換器的峰值效率達到 96%,並在 6 µA 至 1.8 A 的負載電流範圍內維持超過 85% 的效率。其動態負載範圍達到 4×10⁶ (500 nA – 2.0 A),在 0.5 µA 至 1 A 的負載步階變化過程中,電壓下跌為 85 mV(理想電壓跌落的 1.99 倍),且負載瞬態回復時間為 1 µs。
The thesis details three innovative power management integrated circuit (PMIC) designs for system-on-chip (SoC) applications:

Mobile Gaming Applications: This study introduces innovative techniques for current balancing and interleaving in multiphase buck converters. We developed a dual-phase buck converter incorporating a self-subtracted RLG current sensor, achieving a compact design with significant improvements in current sharing accuracy and sensing error. Fabricated in a TSMC 0.18 μm CMOS process, the converter includes a 0.586 mm² total chip area with a dedicated 0.062 mm² area for the current sensor. The design achieves a current balance error within 2.2% for loads between 1 A and 2 A, and a 71% improvement in current sharing accuracy between phases, with a sensing error within 50 mA for loads from 1.2 A to 2.6 A.
Additionally, the introduction of a phase interpolator for interleaving using adaptive on-time control enhanced the dynamic performance and noise immunity of the system. Operating at 3 MHz per phase, it exhibits a maximum jitter of 30.25 ns and a phase error of 7.3 degrees at the ripple cancellation point. The prototype, also using a TSMC 0.18 μm process, occupies a compact 1.41 mm² area (including a 0.03 mm² phase-interpolator section) and achieves a peak efficiency of 95.58%, demonstrating excellent dynamic performance during load transitions with an 80 mV voltage drop and a 2 μs settling time under a 3 A load step.

AIoT Applications: We introduce a DC-DC buck converter with an ultra-low quiescent current of 55 nA, utilizing AOT V2 topology. This converter manages an efficiency of 96% at peak and maintains above 85% across load currents from 6 µA to 1.8A. The dynamic load range extends by 4×10⁶ (500 nA – 2.0 A), with a load transient recovery time of 1 µs and an output voltage drop of 85 mV (1.99X ideal voltage drop) during a loading step change from 0.5 µA to 1 A in 200 ns.
URI: http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/96431
DOI: 10.6342/NTU202500328
Fulltext Rights: 同意授權(限校園內公開)
metadata.dc.date.embargo-lift: 2025-02-14
Appears in Collections:電機工程學系

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