金氧半穿隧二極體之暫態電流行為

Abstract

本篇博士論文深入探討了鋁/二氧化矽/p型矽組成的金屬-氧化層-半導體穿隧二極體（金氧半穿隧二極體）中的暫態電流行為。透過施加不同極性的寫入電壓並以相同電壓讀取，我們發現金氧半穿隧二極體之閘極可讀取到不同極性的暫態電流，可作為動態記憶體之雙態使用。論文前段主要聚焦於平面金氧半穿隧二極體的研究，通過大量實驗數據，我們評估了寫入電壓程式的極性、大小、持續時間及元件氧化層厚度對毫秒時間尺度下暫態電流的影響。實驗中發現，正向寫入電壓增加時，暫態電流會出現飽和現象，這可歸因於在從寫入電壓切換到讀取電壓的瞬間有大量多數載子電洞流入半導體中與儲存的少數載子電子做快速復合。我們透過TCAD模擬深入分析了在整個暫態過程中、包括了毫秒尺度之前的載子運動，並根據電洞流動方向將其分為三個時期：介電層弛豫期、電洞排出期和漂移復合期。我們進一步將漂移復合期這一過程建模，所得模型成功預測暫態電流之飽和電壓，模型分析與TCAD模擬結果的偏差僅為0.01伏。 為提高暫態電流性能，我們探索了薄金屬環繞閘極與氧化層局部薄化等特殊結構。薄金屬環繞閘極金氧半穿隧二極體實現了相較於最佳平面金氧半穿隧二極體4.5倍的暫態電流提升，歸因於薄金屬橫向電阻所造成環繞閘極底下儲存之電子產生的延遲效應。而通過在深空乏條件下施加電應力下引發介電層軟崩潰，可創造出氧化層局部薄化之金氧半穿隧二極體，其暫態電流性能比最佳平面結構提高了20倍，這是由於氧化層局部薄化區域的高穿隧機率會使半導體側在寫入時大量缺少電子，在讀取時將有極強的電子電流流經此一氧化層局部薄化區來補足這一缺額，使得暫態電流大幅提升。 在本論文的附錄中，我們藉助模擬深入探討了氧化層電荷對於平面金氧半穿隧二極體之暫態電流的影響。氧化層電荷會在元件外形成空乏區，加快儲存電子的復合速率，顯著降低毫秒時間尺度的暫態電流。此外，當氧化層電荷較多時會在元件外吸引電子，若施加較大的閘極寫入電壓，將導致元件外部電子匱乏，讀取時需透過載子生成來補充電子，從而產生反向暫態電流。

This dissertation investigates the transient current behavior in Al/SiO2/Si(p) metal-insulator-semiconductor tunnel diodes (MIS tunnel diode, MISTD). By applying write voltages of different polarities and reading at a constant voltage, we discovered that the gate of the MISTD can detect transient currents of varying polarities, which can serve as the two states for dynamic memory applications. The initial part of the dissertation focuses on the Planar MISTD. Using extensive experimental data, we discussed the impact of write voltage polarity, write voltage magnitude, write time, and the oxide layer thickness on the transient current at the millisecond time scale. We observed that with an increase in positive write voltage, the transient current reaches a saturation point. This saturation is attributable to the rapid recombination of holes flooding into the semiconductor with the stored minority carrier electrons upon switching to the read voltage. Through TCAD simulations, we analyzed the movement of carriers during the transient process in the sub-millisecond regime, classifying the motion of holes into three periods: dielectric relaxation period, hole depletion period, and diffusion and recombination period. We further modeled the transient current during the diffusion and recombination period, finding that the modeling results aligned closely with the TCAD simulation results. Additionally, our model successfully predicted the saturation voltage of the transient current, deviating from the TCAD simulation results by only 0.01 volts. To enhance transient current performance, we explored special structures such as the ultra-thin metal surrounded gate (UTMSG) MISTD and oxide local thinning (OLT) MISTD. The UTMSG MISTD achieved a 4.5 times increase in transient current compared to the best Planar device, due to the edge late response effect of the electrons under the surrounding gate caused by the lateral resistance of the thin metal. On the other hand, inducing dielectric soft breakdown under deep depletion stress created an OLT MISTD, which improved transient current performance by 20 times compared to the best Planar device. This improvement is due to the high tunneling probability in the locally thinned oxide region, leading to a significant electron deficiency on the semiconductor side during the write procedure. During reading, a strong electron current flows through this thinned oxide area to compensate for the deficiency, significantly boosting the transient current. In the appendix, we further explore the impact of oxide charges on the transient current of Planar MISTD through simulations. The presence of oxide charges forms a depletion region outside the gate area, accelerating the recombination of stored electrons and significantly reducing the transient current at the millisecond scale. Moreover, an abundance of oxide charges will induce inversion electrons outside the device, leading to an electron deficiency when a larger gate write voltage is applied. During reading, this deficiency necessitates electron supply through carrier generation, thus forming a reverse transient current.