具有時間數位轉換器輔助平行轉換之十位元十六億赫茲雙通道時間交錯管線連續逼近式類比數位轉換器

Abstract

本文提出了一種管線式逐次逼近類比數位轉換器，具有一輔助性的時間至數位轉換器，幫助實現平行轉換技術，提高操作頻率。作為殘值放大器的環形放大器在提供時域量化器信息方面發揮著關鍵作用。這種方法消除了應用平行轉換技術所需的額外複雜電路和電容，從而實現了20% 的取樣率提升。提出的流水線逐次逼近型類比數位轉換器隨後以雙通道配置實現，進一步將操作頻率提高到1.6 GS/s。該ADC 使用28 奈米CMOS 技術製造，以1.6 GS/s 實現44.9 分貝的訊號對雜訊失真比，並在0.9 伏特供應電壓下消耗10.36 毫瓦，產生45.1 fJ/convstep的Walden 性能評價(FoMw)。

This work presents a pipelined SAR ADC with an auxiliary TDC to implement parallel conversion techniques, enhancing the operating frequency. The ring amplifier, functioning as the residue amplifier, has a crucial role of providing information for the time-domain quantizer. This approach eliminates the need for additional complex circuits and capacitors for applying parallel conversion techniques, resulting in 20% sampling rate boost. The proposed pipelined-SAR ADC is later implemented in a two-channel configuration, further increasing the operation frequency to 1.6 GS/s. Fabricated in 28-nm CMOS technology, the ADC achieves 44.9 dB SNDR at 1.6 GS/s and consumes 10.36 mW with a 0.9-V supply, yielding a Walden FOM of 45.1 fJ/conv.-step.