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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 李泰成 | zh_TW |
| dc.contributor.advisor | Tai-Cheng Lee | en |
| dc.contributor.author | 王劭宇 | zh_TW |
| dc.contributor.author | Shao-Yu Wang | en |
| dc.date.accessioned | 2024-04-12T16:13:41Z | - |
| dc.date.available | 2024-04-13 | - |
| dc.date.copyright | 2024-04-12 | - |
| dc.date.issued | 2024 | - |
| dc.date.submitted | 2024-04-10 | - |
| dc.identifier.citation | [1] J. Lagos, B. P. Hershberg, E. Martens, P. Wambacq, and J. Craninckx, “A 1GS/ s, 12b, SingleChannel Pipelined ADC With DeadZoneDegenerated Ring Amplifiers,” IEEE Journal of SolidState Circuits, vol. 54, pp. 646–658, Mar. 2019.
[2] J. Lagos, B. Hershberg, E. Martens, P. Wambacq, and J. Craninckx, “A SingleChannel, 600MS/ s, 12b, RingampBased Pipelined ADC in 28nm CMOS,” IEEE Journal of SolidState Circuits, vol. 54, pp. 403–416, Feb. 2019. [3] B. Razavi, “Design considerations for interleaved adcs,” IEEE Journal of SolidState Circuits, vol. 48, pp. 1806–1817, 2013. [4] C.H. Chan, Y. Zhu, S.W. Sin, U. SengPan, and R. P. Martins, “26.5 a 5.5mw 6b 5gs/s 4×lnterleaved 3b/cycle sar adc in 65nm cmos,” in 2015 IEEE International SolidState Circuits Conference ( ISSCC) Digest of Technical Papers, pp. 1–3, 2015. [5] B. Razavi, Principles of Data Conversion System Design. WileyIEEE Press, 1995. [6] C. C. Lee and M. P. Flynn, “A sarassisted twostage pipeline adc,” IEEE Journal of SolidState Circuits, vol. 46, pp. 859–869, Apr. 2011. [7] S. Jamal, D. Fu, M. Singh, P. Hurst, and S. Lewis, “Calibration of sampletime error in a twochannel timeinterleaved analogtodigital converter,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 51, pp. 130–139, 2004. [8] W. Jiang, Y. Zhu, M. Zhang, C.H. Chan, and R. P. Martins, “A temperaturestabilized singlechannel 1gs/ s 60db sndr sarassisted pipelined adc with dynamic 54 doi:10.6342/NTU202400849 gmrbased amplifier,” IEEE Journal of SolidState Circuits, vol. 55, pp. 322–332, 2020. [9] H.H. Chang, T.C. Lin, and T.C. Lee, “A singlechannel 1gs/ s 7.48enob parallel conversion pipelined sar adc with a varactorbased residue amplifier,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 69, pp. 2021–2025, 2022. [10] B. Hershberg, S. Weaver, K. Sobue, S. Takeuchi, K. Hamashita, and U.K. Moon, “Ring amplifiers for switched capacitor circuits,” IEEE Journal of SolidState Circuits, vol. 47, pp. 2928–2942, 2012. [11] Y. Lim and M. P. Flynn, “A 100 ms/s, 10.5 bit, 2.46 mw comparatorless pipeline adc using selfbiased ring amplifiers,” IEEE Journal of SolidState Circuits, vol. 50, pp. 2331–2341, 2015. [12] K. M. Megawer, F. A. Hussien, M. M. Aboudina, and A. N. Mohieldin, “A systematic design methodology for classabstyle ring amplifiers,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 65, pp. 1169–1173, 2018. [13] B. Hershberg, B. v. Liempd, N. Markulic, J. Lagos, E. Martens, D. Dermit, and J. Craninckx, “3.6 a 6to600ms/ s fully dynamic ringamp pipelined adc with asynchronous eventdriven clocking in 16nm,” in 2019 IEEE International SolidState Circuits Conference ( ISSCC), pp. 68–70, 2019. [14] H.W. Kang, H.K. Hong, S. Park, K.J. Kim, K.H. Ahn, and S.T. Ryu, “A signequalitybased background timingmismatch calibration algorithm for timeinterleaved adcs,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 63, pp. 518–522, 2016. [15] H.J. Hu, Y.S. Cheng, and S.J. Chang, “A 10bit 1gs/ s 2xinterleaved timingskew calibration free sar adc,” in 2019 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5, 2019. 55 doi:10.6342/NTU202400849 [16] C.C. Liu, S.J. Chang, G.Y. Huang, and Y.Z. Lin, “A 10bit 50MS/ s SAR ADC With a Monotonic Capacitor Switching Procedure,” IEEE Journal of SolidState Circuits, vol. 45, pp. 731–740, Apr. 2010. [17] B. Wicht, T. Nirschl, and D. SchmittLandsiedel, “Yield and speed optimization of a latchtype voltage sense amplifier,” IEEE Journal of SolidState Circuits, vol. 39, pp. 1148–1158, July 2004. [18] B. Murmann, “ADC Performance Survey 19972023.” [Online]. Available: https: //web.stanford.edu/~murmann/adcsurvey.html, 2023. [19] S. Baek, I. Jang, M. Choi, H. Roh, W. Lim, Y. Cho, and J. Shin, “10.5 a 12b 600ms/s pipelined sar and 2xinterleaved incremental deltasigma adc with sourcefollowerbased residuetransfer scheme in 7nm finfet,” in 2021 IEEE International SolidState Circuits Conference (ISSCC), vol. 64, pp. 172–174, 2021. [20] L. Wei, Z. Zheng, N. Markulic, J. Lagos, E. Martens, Y. Zhu, C.H. Chan, J. Craninckx, and R. P. Martins, “An auxiliarychannelsharing background distortion and gain calibration achieving >8db sfdr improvement over 4th nyquist zone in 1gs/s adc,” in 2021 Symposium on VLSI Circuits, pp. 1–2, 2021. | - |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/92555 | - |
| dc.description.abstract | 本文提出了一種管線式逐次逼近類比數位轉換器，具有一輔助性的時間至數位轉換器，幫助實現平行轉換技術，提高操作頻率。作為殘值放大器的環形放大器在提供時域量化器信息方面發揮著關鍵作用。這種方法消除了應用平行轉換技術所需的額外複雜電路和電容，從而實現了20% 的取樣率提升。提出的流水線逐次逼近型類比數位轉換器隨後以雙通道配置實現，進一步將操作頻率提高到1.6 GS/s。該ADC 使用28 奈米CMOS 技術製造，以1.6 GS/s 實現44.9 分貝的訊號對雜訊失真比，並在0.9 伏特供應電壓下消耗10.36 毫瓦，產生45.1 fJ/convstep的Walden 性能評價(FoMw)。 | zh_TW |
| dc.description.abstract | This work presents a pipelined SAR ADC with an auxiliary TDC to implement parallel conversion techniques, enhancing the operating frequency. The ring amplifier, functioning as the residue amplifier, has a crucial role of providing information for the time-domain quantizer. This approach eliminates the need for additional complex circuits and capacitors for applying parallel conversion techniques, resulting in 20% sampling rate boost. The proposed pipelined-SAR ADC is later implemented in a two-channel configuration, further increasing the operation frequency to 1.6 GS/s. Fabricated in 28-nm CMOS technology, the ADC achieves 44.9 dB SNDR at 1.6 GS/s and consumes 10.36 mW with a 0.9-V supply, yielding a Walden FOM of 45.1 fJ/conv.-step. | en |
| dc.description.provenance | Submitted by admin ntu (admin@lib.ntu.edu.tw) on 2024-04-12T16:13:41Z No. of bitstreams: 0 | en |
| dc.description.provenance | Made available in DSpace on 2024-04-12T16:13:41Z (GMT). No. of bitstreams: 0 | en |
| dc.description.tableofcontents | 誌謝iii
摘要v Abstract vi Contents vii List of Figures x List of Tables xiii 1 Introduction 1 1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 Thesis Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2 Fundamental 3 2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.2 ADC Performance Metrics . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.2.1 Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.2.2 DNL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.2.3 INL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.2.4 SNR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.2.5 SNDR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.2.6 SFDR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.2.7 ENOB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.2.8 FoM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.3 Introduction of ADC architecture . . . . . . . . . . . . . . . . . . . . . . 7 2.3.1 PipelinedSAR ADC . . . . . . . . . . . . . . . . . . . . . . . . 7 2.3.2 Timeinterleaved ADC . . . . . . . . . . . . . . . . . . . . . . . 8 3 System Architecture and Implementation 12 3.1 Prior PipelinedSAR ADCs . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.2 Ring Amplifier Property . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.2.1 Slewing State . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.2.2 Stabilization state . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.2.3 Steady State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.2.4 Unique Characteristic of Ring Amplifier . . . . . . . . . . . . . . 17 3.3 The Proposed PipelinedSAR Architecture . . . . . . . . . . . . . . . . . 18 3.3.1 Fully Differential Ring amplifier . . . . . . . . . . . . . . . . . . 21 3.3.2 Proposed PDET Circuit . . . . . . . . . . . . . . . . . . . . . . . 23 3.3.3 Delay Line TDC . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.4 Twochannel ADC Design Consideration . . . . . . . . . . . . . . . . . 27 3.4.1 Bootstrapped Switch With Global Clock . . . . . . . . . . . . . . 29 3.5 Other Building Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.5.1 Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.5.2 Capacitor DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.5.3 SAR Control Logic . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.5.4 Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.6 Layout Floor Plan and Simulation Results . . . . . . . . . . . . . . . . . 37 4 Experimental Result 40 4.1 Chip Micrograph . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 4.2 Printed Circuit Board Design . . . . . . . . . . . . . . . . . . . . . . . . 41 4.3 Measurement Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 4.3.1 Basic Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 4.4 Transformer Phase Unbalance . . . . . . . . . . . . . . . . . . . . . . . 43 4.5 Experimental Result . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 4.5.1 Chip 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 4.5.2 Chip 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 4.6 Performance Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 5 Conclusion 51 5.1 Comparison Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 5.2 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Bibliography 54 | - |
| dc.language.iso | en | - |
| dc.subject | 管線式逐次逼近類比數位轉換器 | zh_TW |
| dc.subject | 環形放大器 | zh_TW |
| dc.subject | 平行轉換 | zh_TW |
| dc.subject | 時域量化器 | zh_TW |
| dc.subject | 時間交織類比數位轉換器 | zh_TW |
| dc.subject | parallel conversion | en |
| dc.subject | pipelined-SAR ADC | en |
| dc.subject | time-interleaved ADC | en |
| dc.subject | time-domain quantizer | en |
| dc.subject | ring amplifier | en |
| dc.title | 具有時間數位轉換器輔助平行轉換之十位元十六億赫茲雙通道時間交錯管線連續逼近式類比數位轉換器 | zh_TW |
| dc.title | A 10b 1.6 GS/s 2-Time Interleaved TDC-assisted Pipelined-SAR ADC with Parallel conversion | en |
| dc.type | Thesis | - |
| dc.date.schoolyear | 112-2 | - |
| dc.description.degree | 碩士 | - |
| dc.contributor.oralexamcommittee | 鍾勇輝;林宗賢;陳信樹 | zh_TW |
| dc.contributor.oralexamcommittee | Yung-Hui Chung;Tsung-Hsien Lin;Hsin-Shu Chen | en |
| dc.subject.keyword | 管線式逐次逼近類比數位轉換器,環形放大器,平行轉換,時域量化器,時間交織類比數位轉換器, | zh_TW |
| dc.subject.keyword | pipelined-SAR ADC,ring amplifier,parallel conversion,time-domain quantizer,time-interleaved ADC, | en |
| dc.relation.page | 56 | - |
| dc.identifier.doi | 10.6342/NTU202400849 | - |
| dc.rights.note | 未授權 | - |
| dc.date.accepted | 2024-04-11 | - |
| dc.contributor.author-college | 電機資訊學院 | - |
| dc.contributor.author-dept | 電子工程學研究所 | - |
| 顯示於系所單位： | 電子工程學研究所 | |
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