圖案化4H碳化矽基板上氮化鎵磊晶層之研究

Abstract

隨著現今電子設備和通信系統的進步，對於高頻、高功率和高電壓的要求也提高，而第一代半導體(Si、Ge)和第二代半導體(GaAs、InP)的溫度、頻率和功率也已經達到極限，這時第三代半導體(GaN、SiC)的出現，也使這些瓶頸有了突破，尤以GaN磊晶層搭配SiC基板最令人注目，因此材料系統具備寬能隙、SiC高導熱係數等材料優勢。 本論文致力於圖案化SiC基板之開發，用以減低GaN磊晶層內之缺陷密度。首先，為了探討陰極射線發光技術是否可以作為量測差排的方法，將使用XRD量測技術去探討一般基板之磊晶結構的缺陷密度大小，並說明CL的量測結果是否可以分析差排密度。針對圖案化SiC基板之開發，本論文研發磊晶側向生長法(ELOG)與圖案化4H-SiC基板。透過一系列的製程製造出圖案化的二氧化矽柱，並且使用陰極射線發光技術來量測ELOG法做出來的氮化鎵磊晶層的缺陷密度，以及探討圖案尺寸與差排密度之間的關係。 在使用圖案化4H-SiC基板方法前，本文會先介紹反應式離子蝕刻(RIE)蝕刻4H-SiC的方法，並調整RIE的氣體流量、壓力、功率和時間，以實現事先設計好的圖案和蝕刻深度，隨後進行微縮尺寸的處理。最終，透過本文的探討與研究希望能製造出低缺陷的氮化鎵磊晶層，並期望未來可以應用於高電子遷移率電晶體(HEMT)的製作。

With the advancement of electronic devices and communication systems, the requirements for high frequency, high power, and high voltage have increased. The temperature, frequency, and power limits of the first-generation semiconductors (Si, Ge) and second-generation semiconductors (GaAs, InP) have already been pushed to their limitations. The emergence of third-generation semiconductors has provided breakthroughs in these limitations, especially the combination of GaN epitaxial layers with SiC substrates, which is particularly noteworthy due to the material system's advantages such as wide bandgap and high thermal conductivity of SiC. This work is dedicated to the development of patterned SiC substrates to reduce defect density within GaN epitaxial layers. First, in order to explore whether cathodoluminescence (CL) can serve as a method for measuring dislocation density, X-ray diffraction (XRD) measurement techniques will be used to investigate the defect density of the epitaxial structures, and the CL measurement results will be analyzed to assess dislocation density. For the development of patterned SiC substrates, this study investigates epitaxial lateral overgrowth (ELOG) and patterned 4H-SiC substrates. A series of processes are employed to create patterned silicon dioxide (SiO2) pillars, and the CL technology is utilized to measure the defect density of the GaN epitaxial layers produced by the ELOG method, as well as to explore the relationship between pattern dimensions and dislocation density. Before utilizing the method of patterned 4H-SiC substrates, this work introduces the reactive ion etching (RIE) technique for etching 4H-SiC, adjusting RIE gas flow, pressure, power, and time to achieve pre-designed patterns and etching depths, followed by fine-scale treatment. Ultimately, through the exploration and research presented in this study, the aim is to manufacture low-defect GaN epitaxial layers, with the future expectation of their application in the production of high electron mobility transistors (HEMTs).