一個二階的連續時間型三角積分類比數位轉換器使用九位元迴授

Abstract

本論文提出一個適用於多位元量化器及高解析迴授之連續時間三角積分調變類比至數位轉換器的系統架構。這個提出的架構相比於傳統的方法得以大幅提高迴授之解析度。使用高解析度迴授使得穩定性提升，並降低對於放大器線性度的要求及所需的功耗，且降低時脈抖動的敏感性。 本論文實作了一個使用九個位元整體迴授的連續時間三角積分調變類比至數位轉換器。提出的由主動式電阻電容構成基於比例積分控制器的迴路濾波器、混合式切換的電阻式數位至類比轉換器、及一個最佳化指叉間距之金屬-氧化層-金屬電容，得以實現有效率的實現一個高解析度位元的連續漸進式暫存器之量化器，藉此達成低消耗功率。 此晶片製作於台積電28奈米CMOS標準製程。占用有效面積為0.063平方毫米。此調頻器轉換器在每秒四十百萬次的取樣速度下，於一點二五百萬赫茲的頻寬內量測到訊號對雜訊失真比與動態範圍分別為74.9 dB與76.4 dB，整體只從一個0.9伏的電壓消耗0.36毫瓦的功率，達到Schreier與Walden品質因數分別為170.4 dB與32.2 fJ/conversion-step。

This thesis proposes a system architecture of continuous-time (CT) delta-sigma modulator (DSM) ADC, suitable for multi-bit quantizer (QTZ) and high-resolution feedback. The proposed architecture can significantly increase the feedback resolution compared to the conventional methods. The employment of high-resolution feedback in CT DSM improves stability, reduces the linearity requirements and power consumption of the amplifiers, and mitigates clock jitter sensitivity. A CT DSM ADC utilizing 9-bit feedback is presented. The proposed active-RC proportional-integrator-based loop filter, hybrid switching resistor-DAC, and an optimized metal-oxide-metal capacitor allow for an efficient design of highly multi-bit CT DSM, thereby achieving low power consumption. The prototype chip is fabricated in TSMC 28nm CMOS process and occupies an active area of 0.063mm2. Clocked at 40 MHz, the modulator measures a 74.9 dB SNDR and 76.4 dB dynamic range (DR) within a 1.25 MHz bandwidth while consuming only 0.36 mW from a single 0.9V supply, achieving a FOMS and FOMW of 170.4 dB and 32.2 fJ/conversion-step., respectively.