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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 陳信樹 | zh_TW |
| dc.contributor.advisor | Hsin-Shu Chen | en |
| dc.contributor.author | 吳俊逸 | zh_TW |
| dc.contributor.author | Jun-Yi Wu | en |
| dc.date.accessioned | 2023-07-19T16:08:07Z | - |
| dc.date.available | 2023-11-09 | - |
| dc.date.copyright | 2023-07-19 | - |
| dc.date.issued | 2023 | - |
| dc.date.submitted | 2023-04-07 | - |
| dc.identifier.citation | [1] S. Pavan, R. Schreier and G. Temes, Understanding Delta-Sigma Data Converters, Piscataway, NJ, USA:IEEE Press, 2017.
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Sodini, “A higher order topology for interpolative modulators for oversampling A/D converters,” IEEE Transactions on Circuits and Systems, vol. 37, no. 3, pp. 309–318, 1990. [11] R. Zanbaghi, P. K. Hanumolu and T. S. Fiez, "An 80-dB DR, 7.2-MHz Bandwidth Single Opamp Biquad Based CT ΔΣ Modulator Dissipating 13.7-mW," in IEEE Journal of Solid-State Circuits, vol. 48, no. 2, pp. 487-501, Feb. 2013. [12] T. Song, Z. Cao and S. Yan, "A 2.7-mW 2-MHz Continuous-Time ΣΔ Modulator With a Hybrid Active–Passive Loop Filter," in IEEE Journal of Solid-State Circuits, vol. 43, no. 2, pp. 330-341, Feb. 2008. [13] M. Ortmanns and F. Gerfers, Continuous-time sigma-delta A/D Conversion: Fundamentals Performance Limits and Robust Implementations, New York:Springer-Verlag, 2006. [14] M. Ortmanns, F. Gerfers, and Y. Manoli, “A continuous-time ΔΣ modulator with reduced sensitivity to clock jitter through SCR feedback,” in IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 52, no. 5, pp. 875–884, May 2005 [15] B. M. Putter, “ΔΣ ADC with finite impulse response feedback DAC,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, vol. 1, Feb. 2004, pp. 76–77. [16] M. Keller, A. Buhmann, J. Sauerbrey, M. Ortmanns and Y. Manoli, "A Comparative Study on Excess-Loop-Delay Compensation Techniques for Continuous-Time Sigma–Delta Modulators," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 55, no. 11, pp. 3480-3487, Dec. 2008. [17] L. J. Breems, E. J. van der Zwan, and J. H. Huijsing, “A 1.8-mWCMOS ΔΣ modulator with integrated mixer for A/D conversion of IF signals,” IEEE J. Solid-State Circuits, vol. 35, no. 4, pp. 468–475, Apr. 2000. [18] P. Fontaine, A. N. Mohieldin, and A. Bellaouar, “A low-noise low-voltage CT ΔΣ modulator with digital compensation of excess loop delay,” in Dig. Tech. Papers 2005 IEEE Int. Solid-State Circuits Conf.,vol. 1, pp. 498–613. [19] G. Wei, P. Shettigar, F. Su, X. Yu and T. Kwan, "A 13-ENOB, 5 MHz BW, 3.16 mW multi-bit continuous-time ΔΣ ADC in 28 nm CMOS with excess-loop-delay compensation embedded in SAR quantizer," 2015 Symposium on VLSI Circuits (VLSI Circuits), 2015, pp. C292-C293. [20] I. Galton, "Why Dynamic-Element-Matching DACs Work," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 57, no. 2, pp. 69-74, Feb. 2010. [21] R. T. Baird and T. Fiez, “Linearity Enhancement of Multibit ΔΣ A/D and D/A Converters using Data Weighted Averaging,” IEEE Trans. on Circuits and Systems – II: Analog and Digital Signal Processing, vol. 42, pp. 753–762, December 1995. [22] J. Liu, S. Li, W. Guo, G. Wen, and N. Sun, “A 0.029mm2 17-fJ/conv.-step CT ∆Σ ADC with 2nd-order noise-shaping SAR quantizer,” in 2018 IEEE Symposium on VLSI Circuits, Jun. 2018, pp. 201–202. [23] M. Pietzko, J. Ungethüm, J. G. Kauffman, Q. Li and M. Ortmanns, "Bitwise ELD Compensation in Δ∑ Modulators," 2022 IEEE International Symposium on Circuits and Systems (ISCAS), 2022, pp. 566-570. [24] R. Schreier, The Delta-Sigma Toolbox. [Online]. [25] R. Adams and K. Q. Nguyen, “A 113-dB SNR oversampling DAC with segmented noise shaped scrambling,” IEEE Journal of Solid-State Circuits, vol. 33, no. 12, pp. 1871–1878, 1998. [26] S. -H. Wu, Y. -S. Shu, A. Y. -C. Chiou, W. -H. Huang, Z. -X. Chen and H. -Y. Hsieh, "9.1 A Current-Sensing Front-End Realized by A Continuous-Time Incremental ADC with 12b SAR Quantizer and Reset-Then-Open Resistive DAC Achieving 140dB DR and 8ppm INL at 4kS/s," 2020 IEEE International Solid- State Circuits Conference - (ISSCC), 2020, pp. 154-156. [27] R. Theertham, P. Koottala, S. Billa, and S. Pavan, “A 24 mW chopped CTDSM achieving 103.5dB SNDR and 107.5dB DR in a 250 kHz bandwidth,” in Proc. Symp. VLSI Circuits, Jun. 2019, pp. 1–2. [28] C. -C. Liu, S. -J. Chang, G. -Y. Huang and Y. -Z. Lin, "A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure," in IEEE Journal of Solid-State Circuits, vol. 45, no. 4, pp. 731-740, April 2010. [29] M. Pelgrom, A. C. J. Duinmaijer, and A. Welbers, “Matching properties of MOS transistors,” IEEE J. Solid-State Circuits, vol. 24, no. 5, pp. 1433–1439, 1989. [30] H. Omran, H. Alahmadi and K. N. Salama, "Matching Properties of Femtofarad and Sub-Femtofarad MOM Capacitors," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 63, no. 6, pp. 763-772, June 2016. [31] P. J. A. Harpe et al., "A 26 μW 8 bit 10 MS/s Asynchronous SAR ADC for Low Energy Radios," in IEEE Journal of Solid-State Circuits, vol. 46, no. 7, pp. 1585-1595, July 2011. [32] H. -C. Tsai, C. -L. Lo, C. -Y. Ho and Y. -H. Lin, "A 64-fJ/Conv.-Step Continuous-Time ΣΔ Modulator in 40-nm CMOS Using Asynchronous SAR Quantizer and Digital ΔΣ Truncator," in IEEE Journal of Solid-State Circuits, vol. 48, no. 11, pp. 2637-2648, Nov. 2013. [33] M. van Elzakker, E. van Tuijl, P. Geraedts, D. Schinkel, E. Klumperink, and B. Nauta, “A 1.9 W 4.4 fJ/conversion-step 10 b 1 MS/s charge redistribution ADC,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2008, pp. 244–245. [34] M. Park and M. H. Perrott, "A 78 dB SNDR 87 mW 20 MHz Bandwidth Continuous-Time $\Delta\Sigma$ ADC With VCO-Based Integrator and Quantizer Implemented in 0.13 $\mu$m CMOS," in IEEE Journal of Solid-State Circuits, vol. 44, no. 12, pp. 3344-3358, Dec. 2009. [35] J. L. A. de Melo, J. Goes and N. Paulino, "A 0.7 V 256 μW ΔΣ modulator with passive RC integrators achieving 76 dB DR in 2 MHz BW," 2015 Symposium on VLSI Circuits (VLSI Circuits), Kyoto, Japan, 2015, pp. C290-C291. [36] R. T. Baird and T. S. Fiez, "Linearity enhancement of multibit ΔΣ A/D and D/A converters using data weighted averaging," in IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 42, no. 12, pp. 753-762, Dec. 1995. [37] M. Ortmanns, F. Gerfers and Y. Manoli, "Compensation of finite gain-bandwidth induced errors in continuous-time sigma-delta modulators," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 51, no. 6, pp. 1088-1099, June 2004. | - |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/87725 | - |
| dc.description.abstract | 本論文提出一個適用於多位元量化器及高解析迴授之連續時間三角積分調變類比至數位轉換器的系統架構。這個提出的架構相比於傳統的方法得以大幅提高迴授之解析度。使用高解析度迴授使得穩定性提升，並降低對於放大器線性度的要求及所需的功耗，且降低時脈抖動的敏感性。
本論文實作了一個使用九個位元整體迴授的連續時間三角積分調變類比至數位轉換器。提出的由主動式電阻電容構成基於比例積分控制器的迴路濾波器、混合式切換的電阻式數位至類比轉換器、及一個最佳化指叉間距之金屬-氧化層-金屬電容，得以實現有效率的實現一個高解析度位元的連續漸進式暫存器之量化器，藉此達成低消耗功率。 此晶片製作於台積電28奈米CMOS標準製程。占用有效面積為0.063平方毫米。此調頻器轉換器在每秒四十百萬次的取樣速度下，於一點二五百萬赫茲的頻寬內量測到訊號對雜訊失真比與動態範圍分別為74.9 dB與76.4 dB，整體只從一個0.9伏的電壓消耗0.36毫瓦的功率，達到Schreier與Walden品質因數分別為170.4 dB與32.2 fJ/conversion-step。 | zh_TW |
| dc.description.abstract | This thesis proposes a system architecture of continuous-time (CT) delta-sigma modulator (DSM) ADC, suitable for multi-bit quantizer (QTZ) and high-resolution feedback. The proposed architecture can significantly increase the feedback resolution compared to the conventional methods. The employment of high-resolution feedback in CT DSM improves stability, reduces the linearity requirements and power consumption of the amplifiers, and mitigates clock jitter sensitivity.
A CT DSM ADC utilizing 9-bit feedback is presented. The proposed active-RC proportional-integrator-based loop filter, hybrid switching resistor-DAC, and an optimized metal-oxide-metal capacitor allow for an efficient design of highly multi-bit CT DSM, thereby achieving low power consumption. The prototype chip is fabricated in TSMC 28nm CMOS process and occupies an active area of 0.063mm2. Clocked at 40 MHz, the modulator measures a 74.9 dB SNDR and 76.4 dB dynamic range (DR) within a 1.25 MHz bandwidth while consuming only 0.36 mW from a single 0.9V supply, achieving a FOMS and FOMW of 170.4 dB and 32.2 fJ/conversion-step., respectively. | en |
| dc.description.provenance | Submitted by admin ntu (admin@lib.ntu.edu.tw) on 2023-07-19T16:08:07Z No. of bitstreams: 0 | en |
| dc.description.provenance | Made available in DSpace on 2023-07-19T16:08:07Z (GMT). No. of bitstreams: 0 | en |
| dc.description.tableofcontents | 口試委員審定書 I
致謝 III 摘要 IV Abstract V Contents VI List of Figures X List of Tables XVI Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Thesis Organization 4 Chapter 2 Overview of Delta-Sigma Modulators 5 2.1 Fundamentals of Oversampling Analog-to-Digital Converter 5 2.1.1 Sampling 5 2.1.2 Quantization 8 2.1.3 Decimation 9 2.1.4 Performance Metrics 10 2.2 Delta-Sigma Modulation 12 2.2.1 Noise-Shaping 12 2.2.2 Stability 15 2.2.3 Design Trade-offs and Considerations 17 2.3 Continuous-Time Delta-Sigma Modulator 21 2.3.1 Implementations of CT Modulators 23 2.3.2 Non-Ideal Effects in CT Modulators 24 2.3.3 Compensation of Excess Loop Delay 27 2.3.4 DT versus CT DSM 29 2.4 Mismatch in Feedback DAC 29 2.5 Summary 31 Chapter 3 Proposed Architecture and Techniques Enabling High-Resolution Feedback in CT DSM 32 3.1 Proposed Architecture 32 3.2 Proportional-Integrator-Based Loop Filter 33 3.2.1 Issues of Conventional Topologies in High-Resolution Design 34 3.2.2 Issues of Compensation in High-Resolution Design 36 3.2.3 Proposed Active-RC PI-Based Loop Filter 38 3.2.4 Analysis of System Coefficients 40 3.2.5 SQNR/DR Performance and Integrator Output Swing 43 3.2.6 STF Characteristics 45 3.2.7 Effects of Finite Bandwidth 47 3.3 Hybrid Mismatch Error Shaping (HMES) 50 3.3.1 Segmented Noise-Shaped Scrambling 50 3.3.2 DWA together with Error-Feedback Structure 53 3.3.3 Optimal Design of HMES 56 3.4 Hybrid Switched RDAC 58 3.4.1 Issues of High-Resolution Reference-Switched RDAC 58 3.4.2 Virtual-Ground-Switched RDAC in the Lower Bits 59 3.4.3 Incomplete Signal Reconstruction 61 3.4.4 Supply-line Ripples 64 3.4.5 Power Consumption of Parasitic Capacitors 65 3.5 Optimized Metal-oxide-metal (MOM) Capacitor 66 3.5.1 Input Loading of ASAR QTZ 66 3.5.2 Matching Properties of MOM Capacitor 66 3.5.3 Optimized MOM Spacing 68 3.6 Summary 70 Chapter 4 Design and Implementation of the Proposed 2nd-order CT DSM ADC with 9-bit Feedback 72 4.1 System Design 72 4.1.1 Design Specifications 73 4.1.2 NTF Design 74 4.1.3 Synthesis of CT DSM 76 4.1.4 Ideal Performance 77 4.2 Nonideal Effects 78 4.2.1 Noise Budget 78 4.2.2 Time-constant Variation 79 4.2.3 DAC Nonlinearity 81 4.2.4 ASAR QTZ Nonlinearity 82 4.2.5 Clock Jitter 84 4.2.6 Finite Gain and Bandwidth of Operational Amplifiers 84 4.3 Circuit Implementation 86 4.3.1 Schematic of the Proposed CT DSM 86 4.3.2 Operational Amplifier 87 4.3.3 ASAR Quantizer 89 4.3.4 Feedback RDAC 91 4.3.5 Digital Circuitry for RDAC Linearization 93 4.4 Simulation Results 94 4.4.1 Noise analysis 97 Chapter 5 Experimental Results 98 5.1 Measurement Setup 98 5.1.1 Test Environment 98 5.1.2 Chip Implementation 100 5.2 Measurement Results 100 5.3 Discussions 103 5.3.1 Parasitic Resistance 103 5.3.2 Bond Wire 108 5.3.3 Tone Behavior of DWA 109 5.4 Performance Summary and Comparison 110 Chapter 6 Conclusion and Future Work 112 6.1 Conclusion 112 6.2 Future Work 112 6.2.1 Improvement on the Existing Prototype 112 6.2.2 Further Utilization of High-Resolution Feedback 113 6.2.3 Power Reduction by Compensating for Finite GBW Product 114 Bibliography 119 | - |
| dc.language.iso | en | - |
| dc.title | 一個二階的連續時間型三角積分類比數位轉換器使用九位元迴授 | zh_TW |
| dc.title | A 2nd-order Continuous-Time Delta-Sigma Modulator ADC with 9-bit Feedback | en |
| dc.type | Thesis | - |
| dc.date.schoolyear | 111-2 | - |
| dc.description.degree | 碩士 | - |
| dc.contributor.oralexamcommittee | 陳佳宏;鍾永輝;林宗賢;許雲翔 | zh_TW |
| dc.contributor.oralexamcommittee | Chia-Hung Chen;Yung-Hui Chung;Tsung-Hsien Lin;Yun-Shiang Shu | en |
| dc.subject.keyword | 類比至數位轉換器,連續時間型三角積分調變器,不匹配整型,誤差迴授,連續漸進式暫存器, | zh_TW |
| dc.subject.keyword | analog-to-digital converter,continuous-time delta-sigma modulator,mismatch shaping,error feedback,successive-approximation-register, | en |
| dc.relation.page | 125 | - |
| dc.identifier.doi | 10.6342/NTU202300712 | - |
| dc.rights.note | 同意授權(限校園內公開) | - |
| dc.date.accepted | 2023-04-11 | - |
| dc.contributor.author-college | 電機資訊學院 | - |
| dc.contributor.author-dept | 電子工程學研究所 | - |
| 顯示於系所單位： | 電子工程學研究所 | |
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