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  1. NTU Theses and Dissertations Repository
  2. 電機資訊學院
  3. 電子工程學研究所
請用此 Handle URI 來引用此文件: http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/87718
標題: 製程與量測環境對二硫化錫電子傳輸的效應
Effects of Fabrication Processes and Measurement Ambience on Electron Transport of Tin Disulfide
作者: 吳睿濬
Rui-Jun Wu
指導教授: 李峻霣
Jiun-Yun Li
關鍵字: 二硫化錫,電晶體,變程跳躍,遷移率,
Tin-Sulfide(SnS2),Transistor,Variable-Range-Hopping,Mobility,
出版年 : 2023
學位: 碩士
摘要: 二維金屬硫化物(Metal dichalcogenides, MX2)由於其良好的材料性質和豐富的物理現象(例如:高遷移率、超導性以及強自旋耦合效應)因此受到大量的關注,其中,二硫化錫具有約2.15 ~ 2.76 eV的能隙,被應用在可見光範圍的光電元件上;此外,較高的電子親和力(~ 5.48 eV)亦能應用於高效能穿隧元件。然而,對於二硫化錫的基本性質的研究十分有限,例如:大氣環境如何影響薄膜品質或是低溫載子電性。本論文將研究二硫化錫特性以進一步填補其知識空白。
為了取得高品質的薄膜,我們將二維薄膜轉移系統架設於充滿氮氣的手套箱中,盡量避免製備過程中的氧化效應或環境影響。並分別利用後電極以及預電極製程步驟完成二硫化錫電晶體元件,利用預電極製程步驟製作之電晶體,於溫度100 K下的四點量測電晶體遷移率可達100 cm2/V-s (世界最高)。此外,二硫化錫放置於大氣環境下,閾值電壓變大,可能是因為大氣中的氧氣吸附於二硫化錫表面,並造成P型摻雜,使得遷移率下降、次臨界斜率上升(Subthreshold Slope, SS)以及遲滯加劇(Hysteresis)。
透過變溫量測,利用後電極製程製作之二硫化錫電晶體的電導率隨溫度下降而大幅下降,可利用變程跳躍模型(Variable Range Hopping)解釋,暗示系統受大量的缺陷影響較為無序(disordered),其載子傳輸方式由缺陷間的穿隧所主導。在預電極製程之樣品中,遷移率與溫度的關係則主要受到帶電缺陷以及聲子散射所限,顯示預電極製程有效地提升二硫化錫的遷移率,未來可提供在低溫下量測二硫化錫基本特性的途徑。
Metal dichalcogenides (MX2) are a large family of two-dimensional(2D) materials, which have captured great attention for their excellent material properties and rich physics, such as high mobility, superconductivity, and strong spin-orbit coupling. Among those materials, SnS2 shows great promise for optoelectronics applications in a visible-light range owing to its larger band gap energy of 2.15 ~ 2.76 eV. In additional, its high electron affinity (~ 5.48 eV) allows it to form broken-gap heterostructures for high-performance tunneling devices. However, there has been limited research on carrier transport, ambience effects on the thin film quality, and low-temperature characteristics of SnS2. Therefore, this work aims for bridging the knowledge gap of SnS2.
For high-quality 2D material, the preparation steps to avoid oxidation are crucial. In this work, a nitrogen-filled glove box equipped with a thin-film transfer system is designed and installed for the 2D thin-film preparation. A post-pattern process and a pre-pattern process are used for the fabrication of SnS2 transistors and the effects on the device performance are compared. The highest field-effect mobility of ~ 100 cm2/V-s is demonstrated at 100 K using the pre-pattern process to suppress ambient effects on SnS2 surfaces. Furthermore, a positive shift of the threshold voltage for transistors is observed, attributed to p-type doping effects by oxygen in the atmosphere attached to the SnS2 surface, leading to a worse mobility, a larger subthreshold slope, and serious hysteresis.
Temperature-dependent measurements were performed to characterize the carrier transport in the post-patterned SnS2 transistors. As the temperature decreases, the conductivity is reduced, which follows the Variable-Range-Hopping model. This suggests the disorder in the material dominates and the carrier transport is assisted by electron tunneling between defects. For the pre-patterned device, the temperature dependence of the mobility suggests the charged impurity and phonon scattering dominates. This indicates the pre-pattern process could improve the mobility effectively, paving a way to further explore the fundamental properties of SnS2 at low temperatures.
URI: http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/87718
DOI: 10.6342/NTU202300835
全文授權: 同意授權(全球公開)
顯示於系所單位:電子工程學研究所

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