無電鍍銅之銅-銅熱壓接合與接合面之孔洞演變

Abstract

現今為了滿足人們對電子產品運算效能更好、損耗與更低的需求，三維積體電路(3D ICs)的概念被提出並且被認為是最有希望進一步遵守摩爾定律的封裝技術。3D ICs利用垂直方向地來堆疊晶片，使得此技術能夠同時實現尺寸微縮以及異質整合的優勢，進一步提升接點的數量、降低能耗並縮小晶片面積。在所有作為接點的材料中，銅具有優良的導電性和良好的機械性質，因此被認為是目前最合適的接點材料。除此之外，由於銅-銅的熱壓接合製程簡單且成本要求也低，所以工業界和學術界對此方向已有所研究與開發。然而，在所有製備銅的方法中，無電鍍法具有製程簡單、鍍膜均勻性高及成本低的優勢。無電鍍銅的製程可在大氣環境下進行，且不需使用外部電源，即可利用自催化的行為來大量生產均勻的銅層，這個特性將有利於無電鍍銅在工業量產的應用。因此，本研究意於開發無電鍍銅的銅-銅的熱壓接合技術，希望探索無電鍍銅作為接點材料的可能性。 本研究採用兩種表面的樣品分別為粗糙表面和平坦表面的銅薄膜。表面平坦的銅膜是用來做為研究無電鍍銅成功達成接合所需的最低溫度及接合前與後微結構的演變所需的樣品。而若是為了研究熱處理的參數對孔洞的影響，則選擇使用粗糙的銅膜以便更明顯地觀察孔洞。本研究亦對孔洞隨時間演變的機制做了說明，並透過聚焦離子束及背向電子繞射儀來分析無電鍍銅膜的微結構、結晶取向和晶粒尺寸。除此之外，若要將無電鍍銅作為接點材料，其導電性至關重要，於是本研究也利用范德堡法測量電阻率並與文獻數值比對。總結上述所言，本研究開發了無電鍍銅應用於作為晶片內連線的並使用銅對銅熱壓接合的可能性，也探討了影響接點中位於介面之孔洞的要素，以及其貢獻和演變機制。本研究之無電鍍銅其電阻率相較文獻數值低，也與其他種類的銅之電阻率在相同數量級，因此其有潛力應用於未來晶片封裝的接點材料。此無電鍍銅之銅-銅熱壓接合已成功在250 ℃ 5 MPa 下於15分鐘完成且接合環境要求只需使用機械幫浦所達到的真空度(10-2 torr)。

Since there have been more and more demands on electronic products featured lower consumption and higher performance, people have proposed the concept of three-dimensional integrated circuits (3D ICs). It has been considered as the most encouraging technique for further catching up Moore’s law. With the help of vertically stacking chips, the 3D IC technology allows heterogeneous integration and small form factor as well. Among all materials applied on interconnections of chips, copper spotlights outstanding electrical conductivity and also good mechanical property. Hence, it is considered as the most promising material for chip interconnections. Also, with the replacement of solder, Cu enables fine pitch of interconnections, which can further increase the density of I/O. Moreover, the industry and academia have developed Cu-Cu thermocompression bonding owing to its low-cost requirements and simple process. Copper could be fabricated through many approaches. Among them, electrolessly deposition features the advantages of high uniformity, easy production process and low cost. The characteristic of autocatalytic reaction in electroless plating demonstrates the capability of massively producing uniform Cu layers under atmospheric environment without using exterior electrical energy, which is advantageous from the aspect of convenience and simplicity. Hence, it is worth to develop Cu-Cu bonding technique using electrolessly deposited Cu for future applications on three-dimensional integration. Direct Cu-Cu bonding is well accomplished under 10-2 torr at 250 ℃ 5 MPa for 15 min with the utilization of electrolessly deposited Cu. Numerous effected factors on the voids within bonded joints including surface roughness, bonding temperature, pressure, and time are discussed. In this study, flattened and rough copper blanket layers on silicon substrates were respectively employed to discover the minimum required temperature of Cu-Cu direct thermo-compression bonding, and to inspect the effects of variables during bonding process on interfacial voids. Several variables concerning the shrinkage of voids within joints are studied and the mechanisms are explained. The microstructure, grain size and crystallographic orientation of this electrolessly deposited Cu were also discussed. The electrical resistivity of the electrolessly plated Cu layer was quantified by van der Pauw method. In summary, a novel Cu-Cu thermo-compression bonding using electrolessly fabricated Cu is developed and the process of healing interfacial voids is optimized. Resistivity of the electroless Cu is low enough to be potential material for future chip interconnections. The Cu-Cu thermocompression bonding of electroless Cu is successfully completed at 250 ℃ 5 MPa within 15 min and the bonding environment only requires vacuum reached by mechanical pump (10-2 torr).