請用此 Handle URI 來引用此文件：
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/73006完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 黃俊郎(Jiun-Lang Huang) | |
| dc.contributor.author | Ming-Jhe Li | en |
| dc.contributor.author | 李明哲 | zh_TW |
| dc.date.accessioned | 2021-06-17T07:13:37Z | - |
| dc.date.available | 2020-07-23 | |
| dc.date.copyright | 2019-07-23 | |
| dc.date.issued | 2019 | |
| dc.date.submitted | 2019-07-17 | |
| dc.identifier.citation | [1] G.-H. Hou, “An FPGA-based 200-ps Resolution 16-channel Formatter with Low Resource Usage,” M.S. thesis, National Taiwan University, Taipei, Taiwan, 2018.
[2] W.-C. Huang, “An EG-Pool Based 200-ps Resolution Receiver Implemented on FPGA,” M.S. thesis, National Taiwan University, Taipei, Taiwan, 2018. [3] Quad Pin Timing Formatter ADATE207, Analog Device Inc, 2007. [4] Y.-Y. Chen, “An FPGA-based Sub-nanosecond Low-cost Timing Generator and Formatter,” M.S. thesis, National Taiwan University, Taipei, Taiwan, 2013. [5] P.-C. Shu, “A High Resolution and High Accuracy FPGA Formatter Prototype,” M.S. thesis, National Taiwan University, Taipei, Taiwan, 2014. [6] C.-L. Hsiao, “A High-Resolution FPGA Formatter with Symbol-Stretching and Inversion Capability,” [7] K.-T. Li, “Design and Implementation of 25-ps Resolution, EG-Pool Based Formatter on FPGA,” M.S. thesis, National Taiwan University, Taipei, Taiwan, 2016. [8] Y.-K. Huang, “An FPGA-based Temperature Compensated 200-ps Resolution Multi-channel Formatter,” M.S. thesis, National Taiwan University, Taipei, Taiwan, 2017. [9] A. R. Syed, “RIC/DICMOS - Multi-channel CMOS Formatter,” in International Test Conference, 2003, pp. 175 – 184. [10] A. R. Syed, “Automatic delay calibration method for multichannel CMOS formatter,” in International Test Conference, 2004, pp. 577 – 586. [11] Jaeseok Park, et al. ”Integration of Dual Channel Timing Formatter System for High Speed Memory Test Equipment,” in International SoC Design Conference, 2012, pp. 185 – 187. [12] Luca Mostardini, et al. “FPGA-based Low-cost Automatic Test Equipment for Digital Integrated Circuits,” in International Workshop on Intelligent Data Acquisition and Advanced Computing System: Technology and Applications, 2009, pp. 32 – 37. [13] The Fundamentals of Digital Semiconductor Testing, Soft Test, 2013. [14] C.-A. Lee, “Implementation of High-Resolution and Area-Efficient FPGA Programmable Delay Lines,” M.S. thesis, National Taiwan University, Taipei, Taiwan, 2015. [15] C. Hervé, “High resolution time-to-digital converter (TDC) implemented in field programmable gate array (FPGA) with compensated process voltage and temperature (PVT) variations,” in Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment, 2012, pp. 16 – 25. [16] J. Torre, “Time-to-Digital Converter Based on FPGA With Multiple Channel Capability,” in IEEE Transactions on Nuclear Science, 2014, pp. 107 – 114. [17] Constrains Guide, Xilinx, 2012. [18] Spartan-6 FPGA Configurable Logic Block, Xilinx, 2010. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/73006 | - |
| dc.description.abstract | 自動測試機台(ATE)被使用來測試積體電路(Integrated Circuit, IC)的性能與功能，避免缺陷的IC流入市場。格式器(Formatter)在自動測試機台裡是相當重要的核心模組，其負責讀取使用者定義的符號資料(Symbol Data)，以產生待測電路所需的測試波形。接收器(Receiver)是自動測試機台裡重要的核心模組，其將使用者定義的符號資料、探測時序(Strobe Timing)、理想響應(Golden Response)等資訊組合，以接收待測電路響應(DUT Response)。
在本論文裡，我們提出新的低資源延遲線，並使用特殊的布局方式，將多通道測試器實作於Xilinx Spatan-6 FPGA中，利用約束(Constraint)來輔助設計，我們能大幅降低資源使用量並提高面積使用效率。 最後，本論文實作的16個通道數位積體電路測試器，其具有100 Msps符號產生頻率、積分非線性誤差小於0.5 LSB的高精確度與200 ps邊緣擺置解析度。 | zh_TW |
| dc.description.abstract | Automatic Test Equipment (ATE) is used to test the performance and features of the Integrated Circuit, and avoiding the defective ICs from entering to the market. Format-ter in the ATE is the vital core module to load the symbol data by user’s definition, and then generate the testing waveform for the circuit which should be measured. Receiver is a very important module in ATE, it is responsible for user-defined symbol data, in-cluding strobe timing and golden response to capture the device under test (DUT) re-sponse.
In this paper, it proposes a new delay line with low resource usage, and implements the 16-channel digital IC tester on Xilinx Spatan-6 FPGA board with the special place-ment way. Using relative constraint for aided design, it can improve resource utilization and area usage. At last, the 16-channel digital IC tester implemented in this paper has 100 Msps generation frequency, high accuracy with the integral nonlinearity error less than 0.5 LSB, and 200 ps edge placement resolution. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-17T07:13:37Z (GMT). No. of bitstreams: 1 ntu-108-R06943100-1.pdf: 2382778 bytes, checksum: b1979e9537ab9c4227feff80ec9d2074 (MD5) Previous issue date: 2019 | en |
| dc.description.tableofcontents | 誌謝 i
中文摘要 ii ABSTRACT iii 目錄 iv 圖目錄 vi 表目錄 viii 第1章 緒論 1 1.1 研究動機與目的 1 1.2 相關研究 2 1.3 研究貢獻 3 1.4 論文架構 3 第2章 測試器介紹與先前研究 4 2.1 自動測試機台(Automatic Test Equipment, ATE) 4 2.2 格式器(Formatter) 5 2.3 接收器(Receiver) 7 2.4 先前研究 9 2.4.1 格式器原型架構(Formatter Prototype Architecture) 9 2.4.2 接收器原型架構 11 2.4.3 符號伸展功能 13 2.4.4 邊緣產生器池概念(Edge Generator Pool Concept) 13 2.4.5 可程式化延遲線(Programmable Delay Line) 15 2.4.6 符號資料(Symbol Data)定義、時間設置表和格式設置表 16 第3章 低資源元件設置 19 3.1 可程式化查找表(Programmable Lookup table) 19 3.2 程式塊型(Slice-based)延遲線 21 3.3 作業環境調整 22 第4章 16通道測試器之實作 24 4.1 系統模擬與面積預估算 26 4.2 布局塊模組化(Physical Block Region Modularization) 26 4.3 拼圖(Puzzle)演算法 29 4.4 自動布局布線 32 第5章 實驗結果 34 5.1 實驗環境 34 5.2 多通道測試器之效能分析 35 5.3 測試器之功能驗證 36 5.4 以測試器量測待測電路 39 5.4.1 設置時間 39 5.4.2 保持時間 42 5.5 資源使用量與功率消耗(Resource Utilization & Power Consumption) 44 第6章 結論與未來研究方向 46 6.1 結論 46 6.2 未來研究方向 46 參考文獻 47 | |
| dc.language.iso | zh-TW | |
| dc.subject | 自動測試機台 | zh_TW |
| dc.subject | 多通道格式器 | zh_TW |
| dc.subject | 現場可程式化邏輯閘陣列 | zh_TW |
| dc.subject | 布局演算法 | zh_TW |
| dc.subject | 時序電路 | zh_TW |
| dc.subject | 可程式化延遲線 | zh_TW |
| dc.subject | 接收器 | zh_TW |
| dc.subject | Timing Circuit | en |
| dc.subject | Multi-channel Formatter | en |
| dc.subject | Programmable Delay Line | en |
| dc.subject | Receiver | en |
| dc.subject | FPGA | en |
| dc.subject | Placement Algorithm | en |
| dc.subject | ATE | en |
| dc.title | 於現場可程式化邏輯閘陣列設計與實現數位積體電路測試器 | zh_TW |
| dc.title | Design and Implementation of a 16-channel FPGA-based Digital IC Tester | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 107-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 鄭國興(Kuo-Hsing Cheng),黃炫倫(Xuan-Lun Huang) | |
| dc.subject.keyword | 自動測試機台,多通道格式器,可程式化延遲線,接收器,現場可程式化邏輯閘陣列,布局演算法,時序電路, | zh_TW |
| dc.subject.keyword | ATE,Multi-channel Formatter,Programmable Delay Line,Receiver,FPGA,Placement Algorithm,Timing Circuit, | en |
| dc.relation.page | 48 | |
| dc.identifier.doi | 10.6342/NTU201901572 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2019-07-17 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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