於現場可程式化邏輯閘陣列設計與實現數位積體電路測試器

Abstract

自動測試機台(ATE)被使用來測試積體電路(Integrated Circuit, IC)的性能與功能，避免缺陷的IC流入市場。格式器(Formatter)在自動測試機台裡是相當重要的核心模組，其負責讀取使用者定義的符號資料(Symbol Data)，以產生待測電路所需的測試波形。接收器(Receiver)是自動測試機台裡重要的核心模組，其將使用者定義的符號資料、探測時序(Strobe Timing)、理想響應(Golden Response)等資訊組合，以接收待測電路響應(DUT Response)。 在本論文裡，我們提出新的低資源延遲線，並使用特殊的布局方式，將多通道測試器實作於Xilinx Spatan-6 FPGA中，利用約束(Constraint)來輔助設計，我們能大幅降低資源使用量並提高面積使用效率。 最後，本論文實作的16個通道數位積體電路測試器，其具有100 Msps符號產生頻率、積分非線性誤差小於0.5 LSB的高精確度與200 ps邊緣擺置解析度。

Automatic Test Equipment (ATE) is used to test the performance and features of the Integrated Circuit, and avoiding the defective ICs from entering to the market. Format-ter in the ATE is the vital core module to load the symbol data by user’s definition, and then generate the testing waveform for the circuit which should be measured. Receiver is a very important module in ATE, it is responsible for user-defined symbol data, in-cluding strobe timing and golden response to capture the device under test (DUT) re-sponse. In this paper, it proposes a new delay line with low resource usage, and implements the 16-channel digital IC tester on Xilinx Spatan-6 FPGA board with the special place-ment way. Using relative constraint for aided design, it can improve resource utilization and area usage. At last, the 16-channel digital IC tester implemented in this paper has 100 Msps generation frequency, high accuracy with the integral nonlinearity error less than 0.5 LSB, and 200 ps edge placement resolution.