以現場可程式閘陣列實現之同步動態隨機存取記憶體測試器

Abstract

同步動態隨機存取記憶體(SDRAM)隨著運算量的增加，需求量也隨之成長，找尋便宜的測試方式成為一重要課題。我們希望能找尋低成本的SDRAM測試器，因此本論文提出將SDRAM測試器建置在便宜的現場可程式閘陣列(FPGA)板上，且FPGA板可藉由燒錄方式快速修改測試器的測試目標，不僅降低測試成本也可提供一個多樣性的測試環境。 本論文將記憶體測試機台建置於相對便宜的FPGA板上，並提出三種不同的測試操作方式，包含原始操作法測試方式、一般功能用操作法測試方式、及最佳化測試時間操作方式，三種操作方式皆使用March C-測試圖樣來對SDRAM做測試，且因FPGA板具有可快速重新燒錄的特性，本論文將分析在不同的操作方式下，針對幾項重要時間參數來探討，SDRAM的測試極限所在。

It has been an importance issue in finding a cheap testing method, since the requirement for SDRAM is increasing because of the complex computation. Therefore, we hope to find a cheaper way to replace expensive test station and reduce cost. This thesis proposed an FPGA based SDRAM tester utilizing the characteristic of reconfiguration, it can achieve the low cost and variety test environment at the same time. Establishing the tester on the cheaper tester, this thesis proposed three different test methods, including primitive method, normal mode operation method and optimized operation method. All of the three methods are tested under March C- pattern, and we will analyze the few important parameters under the above mentioned test method to explore the limit of SDRAM.