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標題: | 應用在高速低功耗裝置之九十微米製程類比至數位轉換器之設計 Design of 90nm Analog-to-Digital Converters for Low-Power and High-Speed Applications |
作者: | Chia-Wei Yu 余家緯 |
指導教授: | 陳中平 |
關鍵字: | 類比至數位轉換器,九十微米, Analog-to-Digital Converters,90nm, |
出版年 : | 2014 |
學位: | 碩士 |
摘要: | 管線式類比數位至轉換器和逐漸趨近式類比至數位轉換器已被廣泛地使用在中高解析度且高速的通訊系統中。在本論文中提出了兩個應用於類比數位轉換器的電路設計技術,其中包括管線式類比數位至轉換器和逐漸趨近式類比至數位轉換器,並且透過實際的晶片下線和量測驗證,證實所提出之電路設計技術可以有效提升電路的操作速度,所提出的電路設計技術及晶片實作成果簡述如下:
第一個技術為擁有快速校正技術的管線式類比數位至轉換器,一個高速低功耗的十位元每秒兩億次取樣的管線式類比數位至轉換器,此技術可以利用非常少的高次項校正硬體有效降低百分之五十的校正時間並且不改變通訊系統的設計而達到高解析度、低功耗和高速的類比至數位轉換器。然而,採用1.5位元架構達到高速和降低功耗的設計。此外,提出的校正方法不僅提升了解析度也有效降低運算放大器的增益和頻寬的需求。 本次設計的一個高速低功耗的十位元每秒兩億次取樣的管線式類比數位至轉換器在90微米互補式金氧半電晶體製程下製作,根據量測的結果,本晶片在10MS/s的取樣頻率下,對於1MHz的輸入頻率下SNDR為51dB,SFDR為64.5dB。當時脈升至100MS/s時,SNDR及SFDR分別降為46.7dB及61.6dB。當時脈升至200MS/s時,SNDR及SFDR分別降為46B及60.8dB。電路的消耗功率為20.4mW。 第二個技術為一個九位元操作在每秒一億次取樣的每階段兩位元逐漸趨近式類比至數位轉換器,然而此技術在沒有消耗多餘的功率下有效地增進了操作速度使得逐漸趨近式類比至數位轉換器成為一個高速、低功耗且小面積的類比至數位轉換器。如我們所知,比較器只有高和低兩種結果,所以我們預先準備兩種電壓選擇,因為如此,每一輪比較可以決定兩個位元而不是傳統的一個位元。相較於使用傳統架構的逐漸趨近式類比至數位轉換器,操作速度提升了將近百分之七十,且相較於時間交錯式逐漸趨近式類比至數位轉換器,總取樣電容可以減少百分之二十五。 本次提出的一個九位元每秒一億次取樣的每階段兩位元逐漸趨近式類比至數位轉換器在90微米互補式金氧半電晶體製程下製作,根據量測的結果,本晶片在50MS/s的取樣頻率下,對於20MHz的輸入頻率下ENOB和SFDR為6.77和44.71dB。本晶片在50MS/s的取樣頻率下,當時脈為100MS/s對於20MHz的輸入頻率時,ENOB和SFDR為6.05和45.86dB。在100MS/s的操作頻率之下,電路的消耗功率為2.4mW。 Pipelined analog-to-digital converters (ADCs) and Successive-approximation register (SAR) analog-to-digital converters have been widely utilized in high speed communication system for mid to high resolution. This thesis proposes two circuit design techniques for analog-to-digital converters (ADCs), including pipelined ADC with hybrid calibration and successive-approximation register (SAR) ADC. According to the simulation and measurement results of the proof-of-concept prototypes, the proposed techniques are able to improve the operating speed. The proposed techniques and chip measurement results are sketched as follows: The first technique is a pipelined ADC with hybrid calibration, a high speed and low power 10-bit pipelined ADC with 200MS/s sampling clock. This technique can reduce 50% of original calibration time and cost less hardware in high order calibration without changing communication system to accomplish high resolution, low power, and high speed ADC. Moreover, 1.5-bit architecture is applied to achieve high speed and low power application. Besides, the calibration not only increases the resolution, but also lowers the op-amps requirements of the gain and bandwidth. A 10-bit, 200-MS/s pipelined ADC with the proposed calibration is implemented in a 90-nm 1P9M CMOS technology. According to the measuring results, with 1MHz input frequency, the ENOB and SFDR achieve 8.17 and 64.5dB at 10MS/s. The ENOB and SFDR are reduced to 7.46 and 46.7dB at 100MS/s with 1MHz input frequency. The ENOB and SFDR are reduced to 6.85 and 57.3dB at 100MS/s with 1MHz input frequency. The power consumption is 20.4mW at 200MS/s conversion rate. The second design of SAR ADC utilizes the two-bit per step architecture technique operating at 100MS/s in 90nm to make this design a high speed, low power, and small area ADC(without using excessive power.). As we know, the comparator only outputs high and low voltage, so we prepare these two voltages to choose beforehand. Therefore, we are able to decide two bit in one cycle but not one bit in conventional. Compared to converters that use the conventional architecture, the operating speed is increase by about 70%. But compared to time-interleaved SAR ADC, the total sampling capacitor could be reduced by 25%. A 9-bit, 100-MS/s SAR ADC with the proposed two-bit per step switching procedure is implemented in a 90-nm 1P9M CMOS technology. According to the measuring results with 20MHz input frequency, the ENOB and SFDR achieve 6.77 and 44.71dB at 50MS/s. The ENOB and SFDR are reduced to 6.05 and 45.86dB at 100MS/s with 10MHz input frequency. The power consumption is 2.4mW at 100MS/s conversion rate. |
URI: | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/58129 |
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顯示於系所單位: | 電子工程學研究所 |
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