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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 陳中平 | |
dc.contributor.author | Chia-Wei Yu | en |
dc.contributor.author | 余家緯 | zh_TW |
dc.date.accessioned | 2021-06-16T08:06:31Z | - |
dc.date.available | 2024-06-19 | |
dc.date.copyright | 2014-07-11 | |
dc.date.issued | 2014 | |
dc.date.submitted | 2014-06-19 | |
dc.identifier.citation | [1] B. Razavi, Principles of Data Conversion System Design. Wiley-IEEE Press, 1995.
[2] Rudy van de Plassche, CMOS Integrated Analog-to-Digital and Digital-to-Analog Converters. Kluwer Academic Publishers, 2003. [3] M. Gustavsson, J. Jacob Wikner and N. Nick Tan, CMOS Data Converters for Communications. Kluwer Acadamic Publishers, 2000. [4] D. Johns and K. Martin, Analog Integrated Circuit Design, John Wiley & Sons, New York, 1997. [5] F. Maloberti, Data Converters, Springer, Dordrecht, 2007. [6] S. H. Lewis, H. S. Fetterman, G. F. Griss Jr., R. Ramachandran, and T. R. Viswanathan, 'A 10-b 20-Msample/s analog-to-digital converter,' IEEE J. Solid-State Circuits, vol. 27, pp. 351-358, Mar. 1992. [7] T. Oshima et al., “Fast Nonlinear Deterministic Calibration of Pipelined A/D Converters,” 2008 IEEE MWSCAS, Session C2L-C-1(2008). [8] C. R. Grace, P. J. Hurst, and S. H. Lewis, “A 12-bit 80-Msample/s pipelined ADC with bootstrapped digital calibration,” IEEE J. Solid-State Circuits, vol. 40, no. 5, pp. 1038–1046, May 2005. [9] A. Verma and B. Razavi, ”A 10b 500MHz 55mW CMOS ADC,” IEEE J. Solid-State Circuits, vol. 44, no. 11, pp. 3039-3050, Nov. 2009. [10] X. Wang, P. J. Hurst, and S. H. Lewis, “A 12-bit 20-Msample/s pipelined analog-to-digital converter with nested digital background calibration,” IEEE J. Solid-State Circuits, vol. 39, no. 11, pp.1799–1808, Nov. 2004. [11] S. H. Lewis, H. S. Fetterman, G. F. Griss Jr., R. Ramachandran, and T. R. Viswanathan, 'A 10-b 20-Msample/s analog-to-digital converter,' IEEE J. Solid-State Circuits, vol. 27, pp. 351-358, Mar. 1992. [12] T. Oshima et al., “Fast Nonlinear Deterministic Calibration of Pipelined A/D Converters,” 2008 IEEE MWSCAS, Session C2L-C-1(2008). [13] T. Cho and P. R. Gray, 'A 10-b 20Msample/s 35mW pipelined A/D converter,' IEEE J. Solid-State Circuits, vol. 30, pp. 166-172, Mar. 1995. [14] F. Maloberti, F. Francesoni, P. Malcovati, and O. J. A. P. Nys, ' Design considerations on low-voltage low-power data converters, ' IEEE Trans. Circuits syst. I, vol. 42, pp. 853-863, Nov. 1995. [15] S. H. Lewis and P. R. Gray, 'A pipelined 5-Msamples/s 9-bit analog-to-digital converter,' IEEE J. Solid-State Circuit, vol. SC-22, pp. 954-961, Dec. 1988. [16] D.-L. Shen, “Design of A High-Speed Pipelined A/D Converters with Open-Loop Amplifiers,” Ph.D. dissertation, Graduate Institute of Electrical Engineering, National Taiwan Univ., Taipei, Taiwan, 2007. [17] A. Verma and B. Razavi, ”A 10b 500MHz 55mW CMOS ADC,” IEEE J. Solid-State Circuits, vol. 44, no. 11, pp. 3039-3050, Nov. 2009. [18] E. Siragusa and I. Galton, “A digitally enhanced 1.8-V 15-bit 40-MSamples/s CMOS pipelined ADC,” IEEE J. Solid-State Circuits, vol. 39, pp. 2126–2138, Dec. 2004. [19] I. Mehr and L. Singer, “A 55-mW, 10-bit, 40-Msample/s Nyquist-rate CMOS ADC,” IEEE J. Solid-State Circuits, vol. 35, pp. 318–325, Mar. 2000. [20] A. M. Abo and P. R. Gray, 'A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter,' IEEE J. Solid-State Circuits, vol. 34, pp. 599-606, May 1999. [21] T. Cho, “Low-power, low-voltage, analog-to-digital converter technique using pipelined architectures, “Ph. D. Thesis, University of California, Berkeley, 1995. [22] B.-M. Min, P. Kim, F. W. Bowman III, D. M. Boisvert, and A. J. Aude, “A 69mW 10-bit 80-MSample/s Pipelined CMOS ADC,” IEEE J. Solid-State Circuits, vol. 38, no. 12, pp. 2031-2039, Dec. 2003. [23] C. C. Liu, S. J. Chang, G. Y. Huang, and Y. Z. Lin, “A 10-bit 50-MS/s SAR ADC with a monotonic capacitor switching procedure,” IEEE J. Solid-State Circuits, vol. 45, no.4, pp. 731-740, April 2010 [24] S. Jiang, M. A. Do, K. S. Yeo, and W. M. Lim, “An 8-bit200-MSample/s pipelined ADC with mixed-mode front-end S/H circuit,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 55, no. 6, pp.1430–1440, Jul. 2008. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/58129 | - |
dc.description.abstract | 管線式類比數位至轉換器和逐漸趨近式類比至數位轉換器已被廣泛地使用在中高解析度且高速的通訊系統中。在本論文中提出了兩個應用於類比數位轉換器的電路設計技術,其中包括管線式類比數位至轉換器和逐漸趨近式類比至數位轉換器,並且透過實際的晶片下線和量測驗證,證實所提出之電路設計技術可以有效提升電路的操作速度,所提出的電路設計技術及晶片實作成果簡述如下:
第一個技術為擁有快速校正技術的管線式類比數位至轉換器,一個高速低功耗的十位元每秒兩億次取樣的管線式類比數位至轉換器,此技術可以利用非常少的高次項校正硬體有效降低百分之五十的校正時間並且不改變通訊系統的設計而達到高解析度、低功耗和高速的類比至數位轉換器。然而,採用1.5位元架構達到高速和降低功耗的設計。此外,提出的校正方法不僅提升了解析度也有效降低運算放大器的增益和頻寬的需求。 本次設計的一個高速低功耗的十位元每秒兩億次取樣的管線式類比數位至轉換器在90微米互補式金氧半電晶體製程下製作,根據量測的結果,本晶片在10MS/s的取樣頻率下,對於1MHz的輸入頻率下SNDR為51dB,SFDR為64.5dB。當時脈升至100MS/s時,SNDR及SFDR分別降為46.7dB及61.6dB。當時脈升至200MS/s時,SNDR及SFDR分別降為46B及60.8dB。電路的消耗功率為20.4mW。 第二個技術為一個九位元操作在每秒一億次取樣的每階段兩位元逐漸趨近式類比至數位轉換器,然而此技術在沒有消耗多餘的功率下有效地增進了操作速度使得逐漸趨近式類比至數位轉換器成為一個高速、低功耗且小面積的類比至數位轉換器。如我們所知,比較器只有高和低兩種結果,所以我們預先準備兩種電壓選擇,因為如此,每一輪比較可以決定兩個位元而不是傳統的一個位元。相較於使用傳統架構的逐漸趨近式類比至數位轉換器,操作速度提升了將近百分之七十,且相較於時間交錯式逐漸趨近式類比至數位轉換器,總取樣電容可以減少百分之二十五。 本次提出的一個九位元每秒一億次取樣的每階段兩位元逐漸趨近式類比至數位轉換器在90微米互補式金氧半電晶體製程下製作,根據量測的結果,本晶片在50MS/s的取樣頻率下,對於20MHz的輸入頻率下ENOB和SFDR為6.77和44.71dB。本晶片在50MS/s的取樣頻率下,當時脈為100MS/s對於20MHz的輸入頻率時,ENOB和SFDR為6.05和45.86dB。在100MS/s的操作頻率之下,電路的消耗功率為2.4mW。 | zh_TW |
dc.description.abstract | Pipelined analog-to-digital converters (ADCs) and Successive-approximation register (SAR) analog-to-digital converters have been widely utilized in high speed communication system for mid to high resolution. This thesis proposes two circuit design techniques for analog-to-digital converters (ADCs), including pipelined ADC with hybrid calibration and successive-approximation register (SAR) ADC. According to the simulation and measurement results of the proof-of-concept prototypes, the proposed techniques are able to improve the operating speed. The proposed techniques and chip measurement results are sketched as follows:
The first technique is a pipelined ADC with hybrid calibration, a high speed and low power 10-bit pipelined ADC with 200MS/s sampling clock. This technique can reduce 50% of original calibration time and cost less hardware in high order calibration without changing communication system to accomplish high resolution, low power, and high speed ADC. Moreover, 1.5-bit architecture is applied to achieve high speed and low power application. Besides, the calibration not only increases the resolution, but also lowers the op-amps requirements of the gain and bandwidth. A 10-bit, 200-MS/s pipelined ADC with the proposed calibration is implemented in a 90-nm 1P9M CMOS technology. According to the measuring results, with 1MHz input frequency, the ENOB and SFDR achieve 8.17 and 64.5dB at 10MS/s. The ENOB and SFDR are reduced to 7.46 and 46.7dB at 100MS/s with 1MHz input frequency. The ENOB and SFDR are reduced to 6.85 and 57.3dB at 100MS/s with 1MHz input frequency. The power consumption is 20.4mW at 200MS/s conversion rate. The second design of SAR ADC utilizes the two-bit per step architecture technique operating at 100MS/s in 90nm to make this design a high speed, low power, and small area ADC(without using excessive power.). As we know, the comparator only outputs high and low voltage, so we prepare these two voltages to choose beforehand. Therefore, we are able to decide two bit in one cycle but not one bit in conventional. Compared to converters that use the conventional architecture, the operating speed is increase by about 70%. But compared to time-interleaved SAR ADC, the total sampling capacitor could be reduced by 25%. A 9-bit, 100-MS/s SAR ADC with the proposed two-bit per step switching procedure is implemented in a 90-nm 1P9M CMOS technology. According to the measuring results with 20MHz input frequency, the ENOB and SFDR achieve 6.77 and 44.71dB at 50MS/s. The ENOB and SFDR are reduced to 6.05 and 45.86dB at 100MS/s with 10MHz input frequency. The power consumption is 2.4mW at 100MS/s conversion rate. | en |
dc.description.provenance | Made available in DSpace on 2021-06-16T08:06:31Z (GMT). No. of bitstreams: 1 ntu-103-R00943130-1.pdf: 3287927 bytes, checksum: c52897b86d9b6398ed765bd2d9644e71 (MD5) Previous issue date: 2014 | en |
dc.description.tableofcontents | 口試委員會審定書 i
誌謝 iii 中文摘要 iv ABSTRACT vi CONTENTS viii LIST OF FIGURES xiv LIST OF TABLES xxi Chapter 1 Introduction……………………………………………………………..1 1.1 Motivation 1 1.2 Thesis Organization 2 Chapter 2 Fundamental of Analog-to-Digital Converters 3 2.1 Introduction 3 2.2 ADC Performance metrics 3 2.2.1 Differential Nonlinearity (DNL) 3 2.2.2 Integral Nonlinearity (INL) 4 2.2.3 Signal to Noise Ratio (SNR) 5 2.2.4 Signal-to-(Noise + Distortion) Ratio (SNDR) 7 2.2.5 Resolution and Effective Number of Bits (ENOB) 8 2.2.6 Spurious-Free Dynamic Range (SFDR) 8 2.2.7 Dynamic Range (DR) 9 2.2.8 Figure of Merit (FoM) 10 2.3 Architectures of Analog-to-Digital Converters 10 2.3.1 Flash ADC 10 2.3.2 Two Step and Sub-Ranging ADC 12 2.3.3 Pipelined ADC [6] 13 2.3.4 Cyclic ADC 15 2.3.5 Successive-Approximation (SAR) ADC 16 2.4 Summary 18 Chapter 3 The Proposed Pipelined Analog-to-Digital Converters with Hybrid-Calibration………………………………………………….20 3.1 Introduction 20 3.2 Architecture of Pipelined ADC 22 3.2.1 Architecture of Conventional Pipelined ADC 22 3.2.2 Architecture of the Proposed Pipelined ADC[7] 25 3.2.3 Proposed Analog calibration 30 3.3 Building Block of Proposed pipelined ADC 32 3.3.1 1.5 bits/stage Pipelined ADC Architecture 32 3.3.2 Digital Redundancy and Error Correction 34 3.3.3 Input Sampling Network[17] 37 3.3.4 MDAC conversion stage 39 3.3.1 Digital Calibration [7][8][9][10] 41 3.3.2 Delay Element Circuit 44 3.3.3 Summary 45 3.4 Circuit Implementation and Simulation Results of Proposed Pipelined ADC 46 3.4.1 Introduction 46 3.4.2 Circuit Parameters Designing 46 .3.4.2.1 Capacitor Size Selection 46 3.4.3 Circuit Implementation 49 .3.4.3.1 Switch Technique 49 .3.4.3.2 Operational Amplifier 52 .3.4.3.3 Dynamic Comparator[20][22] 53 3.4.4 Sub-ADC 55 .3.4.4.1 Clock Generator 55 3.4.5 Simulation results 57 3.4.6 Whole chip simulation 57 .3.4.6.1 Post-layout simulation 58 .3.4.6.1.1 Comparison calibration speed between this work and others : 62 3.4.7 Summary 65 3.5Experimental Results and Problems Discussion 66 3.5.1 Introduction 66 3.5.2 Measurement setup 66 3.5.3 PCB Design and Layout Consideration 68 3.5.4 10-bit 200MS/s Pipelined ADC Measurement Result 69 3.5.5 Performance Diagnosis 76 .3.5.5.1 Noise Consideration and Layout Modification 77 .3.5.5.2 THD Improvement with Corner Consideration and Layout Modification 78 .3.5.5.3 PCB Modification for Noise Analysis 79 3.6 Summary 80 Chapter 4 The proposed 2-bit/step SAR Analog-to –Digital converter 82 4.1 Introduction…………………………………………………………………...82 4.2 The proposed 2-bit/step 100MS/s 9-bit SAR ADC 82 4.2.1 Conventional SAR ADC 82 4.2.2 Monotonic SAR ADC[23] 85 4.2.3 Architecture of Proposed SAR ADC 86 4.2.4 Summary 93 4.3 Building Block of Proposed SAR ADC 93 4.3.1 Sample and Hold Circuit[23] 93 4.3.2 Comparator Design 96 4.3.3 Capacitor Array 100 4.3.4 SAR Control Logic 103 4.4 Circuit Implementation and Simulation Results of Proposed SAR ADC 106 4.4.1 Bootstrapped Switch 106 4.4.2 Comparator analysis with Monte-Carlo method 107 4.4.3 Layout and Simulation Results 108 4.4.4 Summary 111 4.5Experimental Results and Problems Discussion 112 4.5.1 Introduction 112 4.5.2 Measurement Environment setup 112 4.5.3 PCB Design and Layout Consideration 114 4.5.4 Experimental results 116 .4.5.4.1 Measurement Results of the chip at 50MS/s 116 .4.5.4.2 Measurement Results of the chip at 100MS/s 117 4.5.5 Performance Diagnosis 119 .4.5.5.1 Layout Implementation Problem 1 (Ref- is Merged with GND) 120 .4.5.5.2 Noisy Common Ground serving as Ref- 120 .4.5.5.3 ESD supply merged with output buffer supply 122 .4.5.5.4 Lack of Clock buffer 123 .4.5.5.5 Summary 125 Chapter 5 Conclusion and Future works 126 5.1 Conclusions 126 5.2 Future work 127 LIST OF FIGURES Chapter 1 Fig. 2 1 DNL transfer curve 4 Fig. 2 2 INL transfer curve 5 Fig. 2 3 Quantization error added to the input obtains the output. 6 Fig. 2 4 The probability distribution function of the quantization noise. 6 Fig. 2 5 SFDR definition. 8 Fig. 2 6 Dynamic range diagram. 9 Fig. 2 7 Architecture of flash ADC 11 Fig. 2 8 Architecture of two step or sub-ranging (K≠1) ADC 12 Fig. 2 9 Architecture of conventional pipelined ADC circuit 15 Fig. 2 10 Block diagram of cyclic ADC. 16 Fig. 2 11 The flow of successive approximation. 17 Fig. 2 12 Architecture of SAR ADC. 18 Fig. 2 13 ADC architectures, applications, resolutions, and sampling rates.[23] 19 Fig. 3 1 (a) Traditional Calibration Method (b) Dithering Method [7] 21 Fig. 3 2 Upward: Dithering Method with only linear Calibration; Downward: Dithering Method with linear and nonlinear Calibration [7] 21 Fig. 3 3 Architecture of conventional 1.5-bit 10 bits pipelined ADC. 23 Fig. 3 4 Timing diagram of pipelined ADC. 24 Fig. 3 5 Architecture with the Proposed Hybrid Calibration Method in PLC System 25 Fig. 3 6 Architecture of the proposed pipelined ADC core. 27 Fig. 3 7 Gain variation diagram of MDAC with low gain OP. 28 Fig. 3 8 The proposed analog calibration circuit in MDAC1. 29 Fig. 3 9 single end ΔVi2 circuit. 29 Fig. 3 10 Comparison between proposed and conventional. 30 Fig. 3 11 Single end (ΔVi)^2 circuit with Vcm bias. 32 Fig. 3 12 Simulation result of proposed circuit between input and output. 32 Fig. 3 13(a)(b) Transfer curve of 1-bit ADC and 1.5-bit ADC. 33 Fig. 3 14 Offset tolerance in a 1.5-bit stage. 35 Fig. 3 15 Error correction in a 1.5-bit stage and a gain-halved 2-bit stage. 36 Fig. 3 16 Process of DEC of a 8 bits pipelined ADC. 37 Fig. 3 17 Architecture of SHA-less with MDAC1. 38 Fig. 3 18 1.5-bit type MDAC conversion stage 39 Fig. 3 19 MDAC sample mode. 40 Fig. 3 20 MDAC evaluation mode. 41 Fig. 3 21 1.5bit MDAC Error Source Diagram 42 Fig. 3 22 Whole Digital Calibration Circuit when Calibration is on 43 Fig. 3 23 Cal. N Block in Fig. 3-22 44 Fig. 3 24 Delay element circuit for 10-bit pipelined ADC. 45 Fig. 3 25 SHA loading condition 47 Fig. 3 26 MDAC loading condition 48 Fig. 3 27 The simplest SHA architecture with NMOS transistor 50 Fig. 3 28 Transmission gate switch. 51 Fig. 3 29 On-resistance diagram of transmission gate 51 Fig. 3 30 op-amp architecture. 53 Fig. 3 31 Layout alignment of pipelined ADC with local bias circuit 54 Fig. 3 32 Sub-ADC & DAC 55 Fig. 3 33 Clock generator. 56 Fig. 3 34 Latch circuit. 57 Fig. 3 35 Clock phases used in pipelined ADC. 57 Fig. 3 36 The floor plan and layout in this work. 59 Fig. 3 37 simulation with 1MHz input and operating at 200MS/s. 60 Fig. 3 38 simulation with 1MHz input and operating at 200MS/s. 61 Fig. 3 39 (b)FF Corner simulation with 1MHz input and operating at 200MS/s. 61 Fig. 3 40 error diagram with the proposed Hybrid- Calibration calibration. 62 Fig. 3 41 error diagram(enlarged version) 63 Fig. 3 42 Measurement setup. 67 Fig. 3 43 Layout of PCB design. 68 Fig. 3 44 Schematic of analog input part. 69 Fig. 3 45 DNL 70 Fig. 3 46 INL 70 Fig. 3 47 10MS/s with 1MHz input frequency 71 Fig. 3 48 20MS/s with 1MHz input frequency 71 Fig. 3 49 40MS/s with 20MHz input frequency 72 Fig. 3 50 100MS/s with 1MHz input frequency 72 Fig. 3 51 200MS/s with 1MHz input frequency 72 Fig. 3 52 200MS/s with 60MHz input frequency 73 Fig. 3 53 The proposed hybrid calibration’s error v.s. learning points 73 Fig. 3 54 20MS/s and 1MHz input frequency with all digital calibration’s FFT 73 Fig. 3 55 All digital calibration’s error v.s. learning points 74 Fig. 3 56 DNL before calibration 76 Fig. 3 57 INL before calibration 77 Fig. 3 58 FFT in 200MS/s without some resisters on voltage references 80 Fig. 3 59 FFT in 200MS/s with some resisters on voltage references 80 Fig. 4 1 Architecture of conventional SAR ADC. 84 Fig. 4 2 Waform of conventional switching procedure. 84 Fig. 4 3 Architecture of monotonic SAR ADC. 86 Fig. 4 4 Flow chart of monotonic SAR ADC. 88 Fig. 4 5 Flow chart of the proposed SAR ADC. 89 Fig. 4 6 The proposed SAR ADC architecture. 90 Fig. 4 7 Proposed switching procedure. 91 Fig. 4 8 Waform of Proposed switching procedure. 92 Fig. 4 9 High linearity bootstrapped switch. 94 Fig. 4 10 The conceptual output waveforms of the bootstrapped circuit 96 Fig. 4 11 Pre-amplifier. 97 Fig. 4 12 Dynamic comparator. 98 Fig. 4 13 Dynamic comparator with a static current source.[23] 99 Fig. 4 14Top view and cross section of multi-layer capacitor 100 Fig. 4 15 the layout of the capacitor array. 101 Fig. 4 16 Tunable delay circuit. 102 Fig. 4 17 Asynchronous control logic. 104 Fig. 4 18 Asynchronous control logic timing diagram. 105 Fig. 4 19 DAC control logic. 105 Fig. 4 20 FFT analysis of SHA output waveform 107 Fig. 4 21 Comparison result. 107 Fig. 4 22 Pre-layout FFT simulation at 100MS/s 108 Fig. 4 23 Post-layout FFT simulation at 100MS/s 109 Fig. 4 24 Corner simulation with 20MHz input. (a) FF (b) SS. 109 Fig. 4 25 Layout alignment of 9-bit 100MS/s work. 111 Fig. 4 26 Measurement setup. 113 Fig. 4 27 Layout of PCB design. 114 Fig. 4 28 Schematic of analog input part. 115 Fig. 4 29 layout the proposed SAR ADC 116 Fig. 4 30 Measuring results of 10-bit 100MS/s SAR ADC. 117 Fig. 4 31 Measuring results of 9-bit 100MS/s SAR ADC 119 Fig. 4 32 Ref- merged with GND operating at 100MS/s. 121 Fig. 4 33 FFT diagram with Ref- merged with GND operating at 100MS/s. 122 Fig. 4 34 Clock through PAD without clock buffer 124 Fig. 4 35 FFT diagram without clock buffer at100MS/s 124 LIST OF TABLES Chapter 3 Table 3 1 Post-layout FFT simulation at 200MS/s 62 Table 3 2 Post-layout comparison 64 Table 3 3 simulation of this work 65 Table 3 4 Measurement result 75 Table 3 5 Measurement result 75 Table 3 6 Measurement result 81 Chapter 4 Table 4 1 Simulation of this work 111 Table 4 2 Simulation of this work 119 | |
dc.language.iso | en | |
dc.title | 應用在高速低功耗裝置之九十微米製程類比至數位轉換器之設計 | zh_TW |
dc.title | Design of 90nm Analog-to-Digital Converters for Low-Power and High-Speed Applications | en |
dc.type | Thesis | |
dc.date.schoolyear | 102-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 李泰成,陳巍仁,張順志,陳少傑 | |
dc.subject.keyword | 類比至數位轉換器,九十微米, | zh_TW |
dc.subject.keyword | Analog-to-Digital Converters,90nm, | en |
dc.relation.page | 132 | |
dc.rights.note | 有償授權 | |
dc.date.accepted | 2014-06-19 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
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