寬頻混合訊號與全數位延遲鎖相迴路暨HomePlug AV2電力線通訊系統收發器

Abstract

在資訊爆炸的時代，為了快速傳遞訊息，資料傳輸扮演著非常重要的腳色，除了需要相當高的傳輸速率外，傳輸過程中的穩定度也十分重要。在本篇論文中，針對在通訊界面中做訊號同步非常重要的延遲鎖相迴路提出了改良，包括一個混合訊號多相位寬頻延遲鎖相迴路與一個全數位低功耗小面積延遲鎖相迴路。另外更完成了一個HomePlug AV2高速電力線通訊系統前端收發器。 在離散式多相位混合訊號延遲鎖相迴路架構中，為了達到寬頻帶操作，本篇論文提出了使用相位插入法，利用相位選擇器偵測操作頻率並提供大部分的延遲時間，再藉由可調式延遲器使輸出相位具有正確延遲時間。此延遲鎖相迴路使用90 nm CMOS製程實現，主要電路面積為0.0644 mm2，在2–8 GHz頻率範圍內皆可正常運作，並分別具有1.93 ps與1.53 ps的相位誤差。 在全數位延遲鎖相迴路中，本論文提出了一個使用相位追蹤延遲器取代傳統冗長延遲線的架構，僅包含兩個閘控環形震盪器，在寬頻帶操作下達到節省晶片面積與功耗的成果。此延遲鎖相迴路經由90 nm CMOS製程實現，操作頻帶為6.7 MHz–1.24 GHz，並僅占0.0318 mm2矽面積，功耗為14.5 mW，其質量因數為0.206，且在任何可操作頻率下，鎖定時間僅需5個周期。在1.24 GHz操作頻率下，此延遲鎖相迴路具有2.22 ps峰對峰相位抖動與424.62 fs均方根相位抖動。 電力線通訊系統從20世紀以來以發展許久，近年來，HomePlug聯盟不斷制定通訊協定，其中以2013年所制定的HomePlug AV2使用1.8–86 MHz通訊頻帶，相較於先前的HomePlug AV使用1.8–28 MHz通訊頻帶，具有更高的資料傳輸速度。本論文也針對HomePlug AV2規格，實現了一個前端收發器，發送端包含一個數位類比轉換器與一個線驅動器，接收端包含一個可變增益放大器與一個類比數位轉換器。此前端收發器使用90 nm CMOS製程實現並達到461 Mbps的傳輸速度。

While the big data generation coming, with the demands of the data communications, a high-speed and robust communication system has become very important. In this thesis, not only a mixed-mode multi-phase distributed delay-locked loop (DDLL) and an all-digital low-power low-cost delay-locked loop (DLL) have been proposed, but also a digital front-end and an analog front-end for HomePlug AV2 high-speed powerline communication (PLC) system has been presented. In the mixed-mode multi-phase DDLL, the phase insertion technique was adopted to achieve wide operating frequencies. The proposed architecture achieves wide operating frequency range by adding a digital phase selector into the DDLL as a coarse-tune block and a automatic frequency detector. The digital phase selector outputs the selected phases according to the detected operating frequency with the most delay for the following tunable delay cells. Thus the selected phases will be fin-tuned by the tunable delay cells for minimizing the phase errors independently. The DDLL was fabricated in 90 nm CMOS technology and occupies 0.0644 mm2 active areas. The operating frequency range is from 2 GHz to 8 GHz, with 1.93 ps and 1.53 ps phase error, respectively. An all-digital DLL (ADDLL) with a phase-tracing delay unit (PTDU) is the second proposed DLL in the thesis to achieve wide operating frequency range, low power and low cost. For the wide-range DLL, the long delay line is replaced by a phase-tracing delay unit (PTDU) which includes two gated ring oscillators (GROs) for generating the wide delay range with a reduced die area. According to the dual loop control scheme in this work, the input clock rising edge and falling edge are tracked independently to ensure that the ADDLL output maintains the duty cycle of the input reference. Furthermore, the ADDLL utilizes an open-loop scheme to achieve fast lock time of 5 clock cycles for all supported input frequencies. The proposed ADDLL has been fabricated in TSMC 90 nm CMOS technology and supports a wide operating frequency range from 6.7 MHz to 1.24 GHz within a small active area of 0.0318 mm2. The measured peak-to-peak and root-mean-square jitter at 1.24 GHz are 2.22 ps and 424.62 fs respectively. The ADDLL consumes 14.5 mW while operating at 1.24 GHz and achieves the FOM of 0.206. A SoC transceiver for the broadband powerline communication system in HomePlug AV2 standard is presented in this thesis. The transceiver consists of a 10-bit 180 MS/s current steering DAC and a line driver with 86 MHz bandwidth, a PGA with a bandwidth in 86 MHz, a 10-bit 180 MS/s pipelined ADC in receiver, and a PLL. In HomePlug AV2, the proposed transceiver achieves 36 dB multi-tone power ratio (MTPR) in the transmitter and 16 dB loopback MTPR in the receiver under 64–QAM constellation map with -23 dB average error vector magnitude (EVM) in 461 Mbps data rate. The transceiver was fabricated in TSMC 90 nm technology and occupies 2.7 mm2 active area. In HomePlug AV2, the transceiver consumes 30 mW, 1.1 W, 25 mW and 16 mW power in DAC, line driver, ADC and PGA.