應用於 STBC MISO/MIMO 正交分頻多工系統之實虛部不匹配 補償與通道等化之聯合演算法及FPGA 設計實作

Abstract

在這篇論文，提出了實虛部不匹配補償及通道等化之結合演算法與實虛部不 匹配自我偵測及校正的演算法。在這個演算法中，IEEE802.11n 的規格將被用來 做為測試的平台。在實虛部不匹配自我偵測及校正的演算法中，是在一啟動使用 者的傳收端時，及立即做自我的振幅及相位的偵測，使得在使用者端，可以大幅 減少實虛部不匹配的影響，並且可以使得載波頻率不匹配的偵測，更加的可靠。 雖然解決了在使用者端的實虛部不匹配及載波頻率不匹配，但由遠端的傳送端所 引起的實虛部不匹配依然存在，因此，實虛部不匹配補償及通道等化之結合演算 法就是用來解決這方面的問題，這個演算法是採用了MMSE 的準則，使得這個 演算法的表現，比LS 的準則，增進了2 dB 左右。 除此之外，在FPGA 的設計上，採用了SR Transformation 來實現實虛部不 匹配補償及通道等化之結合演算法，這個演算法包含了三個部份: 通道估測， MISO/MIMO 信號偵測解碼，以及通道及實虛部不匹配資訊之更新; 經過簡化後， 可以減少35%的乘法複雜度。並且可以達到與未經簡化之前的演算法，有相同 SER 的表現。 最後，經過改良後的複數乘法器設計以及適當的記憶體安排，實現此演算法。 在FPGA 的測量上，是透過Altera Stradix EP1S80 FPGA 板，並在Tektronix TLA 715 邏輯分析儀量測，來驗證此演算法的可行性及正確性。

In this thesis, the joint I/Q imbalance compensation and channel equalization and the start up self-calibration algorithm of I/Q imbalance are proposed. The IEEE 802.11n MISO/MIMO OFDM transceiver is adopted as a test vehicle to demonstrate the presented algorithm. The self-calibration algorithm is performed at transceiver start-up to estimate the end user I/Q imbalance parameter, including phase and gain mismatch. Therefore, the Tx/Rx I/Q imbalance of end user can be alleviated by self calibration and compensation. In addition, the start-up self calibration and compensation can make conventional CFO estimation and compensation more reliable under end user Rx I/Q imbalance impairment. Although Rx I/Q imbalance self compensation and CFO have been compensated, the remote Tx I/Q imbalance and quasi-static channel variation degrade the system performance. Therefore, based on MMSE criteria, the joint I/Q imbalance compensation and channel equalization is presented to minimize the remote Tx I/Q imbalance and quasi-static channel variation during the physical data transmission. Consequently, the performance improvement is 2-dB compared with LS algorithm. On the other hand, the cost-e cient architecture of joint I/Q imbalance compensation and channel equalization is proposed to reduce hardware complexity based on strength-reduced transformation. The cost e cient architecture of joint I/Q imbalance and channel equalization contains three parts: MIMO detection, updating process and channel estimation. The overall architecture obtains the 35% reduction e ciency in multiplication. Furthermore, The uncoded SER of this design is the same as the direct implementation. Finally, the joint I/Q imbalance compensation and channel equalization is realized by FPGA board EP1S80 at 40MHz and the system evaluations are measured by Tektronix TLA715 pattern generator and logic analyzer.