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Title: | 自我振盪式展頻時脈產生器的設計與分析 The Design and Analysis of a Self-Oscillating Spread Spectrum Clock Generator |
Authors: | Chien-Heng Wong 翁健恆 |
Advisor: | 李泰成(Tai-Cheng Lee) |
Keyword: | 展頻時脈產生器,鎖相迴路, SSCG,PLL, |
Publication Year : | 2011 |
Degree: | 碩士 |
Abstract: | 由於金氧半電晶體製程的進步,現今的消費性電子將越來越多的應用都實做在單一晶片上。但由於傳輸的訊號越來越高頻,使得來自傳輸信號的電磁干擾逐漸成為一個重要的課題。除了使用成本較高的直接遮蔽方法來降低電磁波的干擾之外,另一種被稱為”展頻時脈”的方法因為可以整合在電路上而成本較低,所以也被廣泛應用。
展頻時脈本身為一頻率調變的訊號,因此可將載波上的能量分散至某一特定的頻帶進而達到減少電磁干擾的目的。有許多的實作展頻時脈的方法已經被提出,包括直接對電壓控制震盪器做調變、藉由三角積分器來做調變,以及使用開迴路的方法直接產生展頻時脈。這些方法都是藉由加入額外的調變訊號來產生展頻時脈。在此篇論文中,一個使用自我震盪技術、6 GHz、以鎖相迴路為基礎的展頻時脈產生器被提出。此展頻時脈產生器使用了一個一階的迴路濾波器使得整個鎖相迴路系統成現不穩定的狀態而震盪。藉由晶片上對震盪頻率與震盪震幅即時做運算與校正,再不加入額外量化雜訊的前提之下,使得展頻時脈產生器可以產生調變頻率為31.5 kHz、頻率變化量為5000 ppm的展頻訊號。本篇論文之展頻時脈產生器佔用了0.54 mm2、在1.2伏特的供給電壓之下花費了14.4 mW、並且實做於90 nm之數位CMOS製程。此展頻時脈產生器在開啟展頻模式之後能降低12.49 dB的能量。 According to the progress of the MOS process, the architecture of SoC is widely adopted in consumer electronic products nowadays. But the EMI caused by blocks in SoC has become an important issue especially for high-frequency signal transmission. Despite the high-cost method shielding the chip directly, other method such as SSCG which can be integrated on the chip becomes a popular and low-cost way to reduce the EMI. The SSC is a frequency-modulated signal; as a result, it spreads the power of the carrier frequency within specific BW and accomplishes the EMI reduction. Many techniques implementing SSC had been proposed including direct modulating on VCO, sigma-delta modulation, and open-loop method. Almost proposed methods generate SSC by adding extra modulating signal. In this thesis, a 6G-Hz PLL-based SSCG with self-oscillating technique is proposed. The PLL uses a 1st-order loop filter to make VCO control-line oscillate itself while introducing no extra quantization noise. With on-chip calculation and adjusting, modulating frequency will operate at 31.5-kHz and spectrum spread is 5000ppm. This work is fabricated in 90nm digital CMOS technology, occupies 0.54mm2 and consumes 14.4mW from a 1.2V supply. EMI reduction is 12.49dB. |
URI: | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/48354 |
Fulltext Rights: | 有償授權 |
Appears in Collections: | 電機工程學系 |
Files in This Item:
File | Size | Format | |
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ntu-100-1.pdf Restricted Access | 6.82 MB | Adobe PDF |
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