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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 李泰成(Tai-Cheng Lee) | |
dc.contributor.author | Chien-Heng Wong | en |
dc.contributor.author | 翁健恆 | zh_TW |
dc.date.accessioned | 2021-06-15T06:53:39Z | - |
dc.date.available | 2013-02-20 | |
dc.date.copyright | 2011-02-20 | |
dc.date.issued | 2011 | |
dc.date.submitted | 2011-02-11 | |
dc.identifier.citation | [1] H.-H. Chang, I.-H. Hua and S.-I. Liu, “A Spread-Spectrum Clock Generator With Triangular Modulation,” IEEE J. of Solid-State Circuits, vol. 38, pp. 673-676, Apr., 2003.
[2] Y.-B. Hsieh and Y.-H. Kao, “A Fully Integrated Spread-Spectrum Clock Generator by Using Direct VCO Modulation,” IEEE Trans. Circuits Syst. I, vol. 55, pp. 1845-1853, Aug., 2008. [3] D. De Caro, et al., “A 1.27 GHz, All-Digital Spread Spectrum Clock Generator/Synthesizer in 65 nm CMOS,” IEEE J. of Solid-State Circuits, vol. 45, pp. 1048-1060, May, 2010. [4] S. Damphousse, et al., “All Digital Spread Spectrum Clock Generator for EMI Reduction,” IEEE J. of Solid-State Circuits, vol. 42, pp. 145-150, Jan., 2007. [5] M. Kokubo, et al., “Spread-Spectrum Clock Generator for Serial ATA using Fractional PLL Controlled by ΔΣ Modulator with Level Shifter,” ISSCC. Dig. Tech. Papers, Feb., 2005, pp. 160-161. [6] S.-Y. Lin and S.-I. Liu, “A 1.5 GHz All-Digital Spread-Spectrum Clock Generator,” IEEE J. of Solid-State Circuits, vol. 44, pp. 3111-3119, Nov., 2009. [7] F. Pareschi, et al., “A 3 GHz Spread Spectrum Clock Generator for SATA Applications Using Chaotic PAM Modulation,” Proc. IEEE Custom IC Conf., Sept., 2008, pp. 451-454. [8] H.-R. Lee, et al., “A Low-Jitter 5000ppm Spread Spectrum Clock Generator for Multi-channel SATA Transceiver in 0.18μm CMOS,” ISSCC. Dig. Tech. Papers, Feb., 2005, pp. 162-163. [9] J. Shin, et al., “A Low-Jitter Added SSCG with Seamless Phase Selection and Fast AFC for 3rd Generation Serial-ATA,” Proc. IEEE Custom IC Conf., Sept., 2006, pp. 409-412. [10] T. Ebuchi, et al., “A 125–1250 MHz Process-Independent Adaptive Bandwidth Spread Spectrum Clock Generator With Digital Controlled Self-Calibration,” IEEE J. of Solid-State Circuits, vol. 44, pp. 763-774, Mar., 2009. [11] D.-S. Shen and S.-I. Liu, “A Low-Jitter Spread Spectrum Clock Generator Using FDMP,” IEEE Trans. Circuits Syst. II, vol. 54, pp. 979-983, Nov., 2007. [12] C.-Y. Yang, C.-H. Chang and W.-G. Wong, “A Δ-Σ PLL-Based Spread-Spectrum Clock Generator With a Ditherless Fractional Topology,” IEEE Trans. Circuits Syst. I, vol. 56, pp. 51-59, Jan., 2009. [13] Y.-B. Hsieh and Y.-H. Kao, “A New Spread Spectrum Clock Generator for SATA Using Double Modulation Schemes,” Proc. IEEE Custom IC Conf., Sept., 2007, pp. 297-300. [14] B. De Muer and M. Steyaert, “A CMOS Monolithic ΔΣ-Controlled Fractional-N Frequency Synthesizer DCS-1800,” IEEE J. Solid-State Circuits, vol. 37, pp. 835-844, July 2002. [15] W. Rhee, B. Song, and A. Ali, “A 1.1 GHz CMOS Fractional-N Frequency Synthesizer with A 3-b Third-Order ΔΣ Modulator,” IEEE J. Solid-State Circuits, vol. 35, pp. 1453-1460, Oct. 2000. [16] M. Kozak and I. Kale, “Rigorous Analysis of Delta–Sigma Modulators for Fractional-N PLL Frequency Synthesis,” IEEE Trans. Circuits Syst. I, vol. 51, pp. 1148-1162, June 2004. [17] M. H. Perrott, “Fast and Accurate Behavioral Simulation of Fractional-N Frequency Synthesizers and Other PLL/DLL Circuits,” Proc. IEEE 39th Annu. Design Automation Conf., 2002, pp. 498-503. [18] M. H. Perrott, M. D. Trott, and C. G. Sodini, “A Modeling Approach for - Fractional-N Frequency Synthesizers Allowing Straightforward Noise Analysis,” IEEE J. Solid-State Circuits, vol. 37, pp. 839-849, Aug. 2002. [19] T.-H. Lee and A. Hajimiri, “Oscillator Phase Noise: A Tutorial,” IEEE J. Solid-State Circuits, vol. 35, pp. 326-336, Mar. 2000. [20] D. Ham and A. Hajimiri, “Concepts and Methods in Optimization of Integrated LC VCOs,” IEEE J. Solid-State Circuits, vol. 36, pp. 896-909, Jun. 2001. [21] A. Hajimiri and T.-H. Lee, “A General Theory of Phase Noise in Electrical Oscillators,” IEEE J. Solid-State Circuits, vol. 33, pp. 179-194, Feb. 1998. [22] M. Mansuri and C.-K. K. Yang, “Jitter optimization Based on Phase-Locked Loop Design Parameters,” IEEE J. Solid-State Circuits, vol. 37, pp. 1375-1382, Nov. 2002. [23] H. Sjoland, “Improved Switched Tuning of Differential CMOS VCOs” IEEE Trans. Circuits Syst. II, vol. 49, pp. 352-355, May 2002. [24] P. Andreani and S. Mattisson, “On the Use of MOS Varactor in RF VCO’s,” IEEE J. Solid-State Circuits, vol. 35, pp. 905-910, Jun. 2000. [25] B. Razavi, Design of Analog CMOS Integrated Circuirs, McGraw-Hill, 2001. [26] B. Razavi, RF Microelectronics, Prentice Hall, 2003. [27] B. Razavi, Design of Integrated Circuits for Optical Communications, 1st Ed., McGraw-Hill, 2003. [28] D. Johns and K. Martin, Analog Integrated Circuit Design, 1st Ed., [29] 劉深淵與楊清淵, 鎖相迴路, 滄海書局, 2006. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/48354 | - |
dc.description.abstract | 由於金氧半電晶體製程的進步,現今的消費性電子將越來越多的應用都實做在單一晶片上。但由於傳輸的訊號越來越高頻,使得來自傳輸信號的電磁干擾逐漸成為一個重要的課題。除了使用成本較高的直接遮蔽方法來降低電磁波的干擾之外,另一種被稱為”展頻時脈”的方法因為可以整合在電路上而成本較低,所以也被廣泛應用。
展頻時脈本身為一頻率調變的訊號,因此可將載波上的能量分散至某一特定的頻帶進而達到減少電磁干擾的目的。有許多的實作展頻時脈的方法已經被提出,包括直接對電壓控制震盪器做調變、藉由三角積分器來做調變,以及使用開迴路的方法直接產生展頻時脈。這些方法都是藉由加入額外的調變訊號來產生展頻時脈。在此篇論文中,一個使用自我震盪技術、6 GHz、以鎖相迴路為基礎的展頻時脈產生器被提出。此展頻時脈產生器使用了一個一階的迴路濾波器使得整個鎖相迴路系統成現不穩定的狀態而震盪。藉由晶片上對震盪頻率與震盪震幅即時做運算與校正,再不加入額外量化雜訊的前提之下,使得展頻時脈產生器可以產生調變頻率為31.5 kHz、頻率變化量為5000 ppm的展頻訊號。本篇論文之展頻時脈產生器佔用了0.54 mm2、在1.2伏特的供給電壓之下花費了14.4 mW、並且實做於90 nm之數位CMOS製程。此展頻時脈產生器在開啟展頻模式之後能降低12.49 dB的能量。 | zh_TW |
dc.description.abstract | According to the progress of the MOS process, the architecture of SoC is widely adopted in consumer electronic products nowadays. But the EMI caused by blocks in SoC has become an important issue especially for high-frequency signal transmission. Despite the high-cost method shielding the chip directly, other method such as SSCG which can be integrated on the chip becomes a popular and low-cost way to reduce the EMI.
The SSC is a frequency-modulated signal; as a result, it spreads the power of the carrier frequency within specific BW and accomplishes the EMI reduction. Many techniques implementing SSC had been proposed including direct modulating on VCO, sigma-delta modulation, and open-loop method. Almost proposed methods generate SSC by adding extra modulating signal. In this thesis, a 6G-Hz PLL-based SSCG with self-oscillating technique is proposed. The PLL uses a 1st-order loop filter to make VCO control-line oscillate itself while introducing no extra quantization noise. With on-chip calculation and adjusting, modulating frequency will operate at 31.5-kHz and spectrum spread is 5000ppm. This work is fabricated in 90nm digital CMOS technology, occupies 0.54mm2 and consumes 14.4mW from a 1.2V supply. EMI reduction is 12.49dB. | en |
dc.description.provenance | Made available in DSpace on 2021-06-15T06:53:39Z (GMT). No. of bitstreams: 1 ntu-100-R97943107-1.pdf: 6985849 bytes, checksum: 76ee15858c7aef94abaa12af675ab873 (MD5) Previous issue date: 2011 | en |
dc.description.tableofcontents | 口試委員審定書(中/英)
誌謝 i 摘要 iii Abstract iv Contents v List of Figures vii Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Thesis Overview 2 Chapter 2 Elements of Phase-Locked Loop 3 2.1 Introduction 3 2.2 Phase-Locked Loop 3 2.2.1 Simple PLL topology 3 2.2.2 Linear model of PLL 6 2.2.3 Dynamics of PLL 11 2.2.4 Noise Response of PLL 13 Chapter 3 A Self-Oscillating Spread Spectrum Clock Generator 19 3.1 Introduction 19 3.2 System Architecture 21 3.2.1 Adjusting the modulating frequency and amplitude 21 3.2.2 Calculating the modulating frequency and amplitude 24 3.2.3 Architecture of the system 26 3.3 Nonidealty And Design Considerations 31 3.3.1 CN inaccuracy 31 3.3.2 Jitter estimation 33 3.4 Behavioral Simulation 37 Chapter 4 Circuit Implementation 41 4.1 Introduction 41 4.2 Circuit Implementation 41 4.2.1 Phase Frequency Detector (PFD) 41 4.2.2 Charge Pump (CP) 43 4.2.3 Voltage-Controlled Oscillator (VCO) 45 4.2.4 Divide-by-300 Divider 47 4.2.5 SGN 49 4.2.6 Digital Portion 51 4.3 Simulation Results 51 Chapter 5 Experimental Results 53 5.1 Introduction 53 Bibliography 57 Biography 61 | |
dc.language.iso | en | |
dc.title | 自我振盪式展頻時脈產生器的設計與分析 | zh_TW |
dc.title | The Design and Analysis of a Self-Oscillating Spread Spectrum Clock Generator | en |
dc.type | Thesis | |
dc.date.schoolyear | 99-1 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 林宗賢(Tsung-Hsien Lin),劉深淵(Shen-Iuan Liu),陳巍仁(Wei-Zen Chen) | |
dc.subject.keyword | 展頻時脈產生器,鎖相迴路, | zh_TW |
dc.subject.keyword | SSCG,PLL, | en |
dc.relation.page | 62 | |
dc.rights.note | 有償授權 | |
dc.date.accepted | 2011-02-12 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電機工程學研究所 | zh_TW |
顯示於系所單位: | 電機工程學系 |
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ntu-100-1.pdf 目前未授權公開取用 | 6.82 MB | Adobe PDF |
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