利用原子層沉積系統於不同基材上製備氧化鋅薄膜之微結構分析

Abstract

近年來，由於氧化鋅(zinc oxide)具有相當吸引人之物理特性上而因此受到大的關注。而此研究中則是著重於觀察以原子層沉積之技術在不同的基材上(如:矽晶(silicon)，玻璃以及氧化鋁(sapphire))所鍍出的氧化鋅薄膜並觀察薄膜與基材間之界面結構。分析式電鏡，X光繞射，片電阻率，以及光激發螢光…等等，皆為此研究中所採用之分析方法。 明顯的，無論於何種基材上，所鍍出之氧化鋅薄膜都具有許多Moiré條紋以及結構缺陷。由於在氧化鋅及單晶矽間存在著一層氧化矽而使得薄膜與基材間之界面並不平坦，但沉積在氧化鋁基材上的氧化鋅與基材間之界面則是相當平整。氧化鋅薄膜與氧化鋁基材具有相當良好之磊晶方位關係，因此，氧化鋁較單晶矽適合作為氧化鋅磊晶成長之基材，但同時也發現，在氧化鋅/ 氧化鋁之界面上存在著許多由兩者晶格常數之差異所形成的錯位差排。然而，即使氧化鋅薄膜與單晶矽或玻璃基材間不具有磊晶之關係，卻也因為不需考慮薄膜與基材兩者晶格常數之差異問題而在界面具有較低的缺陷密度。在片電阻率及光激發螢光之光譜實驗結果中，我們發現在單晶矽上成長之氧化鋅薄膜較在氧化鋁上成長者具有較佳之電性及光學性質。此可能是因為與氧化鋅/單晶矽的界面相比，在氧化鋁與氧化鋅薄膜之界面上具有較高之缺陷密度所造成的結果。

Zinc oxide (ZnO) has physical properties which has earned it great attention in recent years. This study focuses on the observation of ZnO thin film grown by atomic layer deposition (ALD) technique on various substrates (such as silicon (Si), glass, and sapphire (Al2O3)) and the interface structure between film and substrate. HR-TEM, XRD, sheet resistivity, PL, etc. are the means used to study these samples. It is obvious that ZnO films contain many Moiré fringes and structure defects, regardless of the type of substrate on which they are deposited. ZnO/silicon interfaces are not flat due to the presence of silicon oxide, while ZnO/sapphire interfaces are flat, sharp, and smooth. There are good epitaxial orientation relationships between ZnO thin films and sapphire substrates. Sapphire is a better substrate for ZnO film epitaxy, but at the interface, a number of misfit dislocations still exist due to the lattice mismatch between ZnO and sapphire. Although there are no epitaxial relationships between the films and silicon (or glass) substrates, it is an advantage that there is no lattice mismatch problem between films and silicon or glass substrates, so the density of misfit dislocations at the interface is low.Sheet resistivity and PL spectra show better electrical and optical properties for ZnO thin films grown on silicon instead of on sapphire; one possible reason is that the density of defects at the ZnO/ sapphire interfaces is much higher than at the ZnO/ silicon interfaces.