CMOS位移電容感測器之電路設計

Abstract

本論文的目的在於實現CMOS位移電容感測器之佈局，並比較佈局前後效能之差異。文中利用雙級運算放大器做為主體，接著佈局離散元件，並在佈局後些微修改以達到需求，最後探討全系統架構模擬之電容改變量與輸出電壓間的關係，本系統模擬後解析度可達 法拉等級。 而本論文使用國家晶片系統設計中心(NSC Chip Implementation Center, CIC)所提供的台灣積體電路(TSMC)0.35μm Mixed-Signal 2P4M Polycide 3.3/5V的製程，並使用Synopsys 公司所出的Hspice電路模擬軟體與思源公司的laker軟體進行模擬及佈線。

The purpose of this dissertation is to realize the design and layout of CMOS capacitive sensing circuit, and in this case to compare the differences before and after layout. In this dissertation use the two-stage amplifier to be the principal. Furthermore, layout the dispersed elements, and modify that after layout to satisfy our requirement. This dissertation is applying 0.35μm Mixed-Signal 2P4M Polycide 3.3/5V manufacture process of TSCM which is provided by NSC Chip Implementation Center. Finally, using Hspice software designed by Synopsys co. to simulate and laker software designed by Springsoft co. to layout.