一個高速採用時間交錯式的連續漸進式類比至數位轉換器

Abstract

在次世代無線通訊系統中，類比至數位轉換器必須操作在極高速的取樣頻率及低中解析度下。 本論文提出一個以40奈米CMOS一般製程，實現出六位元每秒四十五億次取樣的時間交錯連續漸進式類比至數位轉換器，藉由結合前端輸入緩衝器的架構及分組式技巧，有效地降低時間交錯式架構的輸入電容負載，並增加輸入訊號的可用安定時間，提出的16通道的時間交錯連續漸進式類比至數位轉換器得以達到高取樣速度及高輸入頻寬的表現。透過使用零交越 (zero-crossing) 偵測技巧，可以補償多通道間時間偏移的誤差，並透過數位校正處理多通道間的增益電壓及偏移電壓不匹配。在單通道方面，採用連續漸進式架構，並使用非同步處理及單向電容切換技巧使單通道具有高速度及高能量效率的特性。除此之外，任意選擇權重之電容陣列解決了單通道中比較器的動態偏移電壓的問題。 量測結果顯示，在每秒四十億的轉換，DNL和INL分別為+0.17/-0.29 LSB和+0.20/-0.18 LSB。在每秒四十五億的轉換及輸入頻率為一億赫茲下，SNDR和SFDR分別為32.15 dB和41.04 dB，在1.2 V的供應電壓下，功率消耗為24.9毫瓦，品質因數(FoM)為159 fJ/c.-s。全部的晶片面積大小為1.275 mm2，核心電路的面積是0.195平方毫米。

Analog-to-digital converter (ADC) has to operate at ultra-high speed with low to medium resolution in the next-generation wireless communication systems. A 6-bit 4.5 GS/s time-interleaved SAR ADC in 40 nm CMOS general–process (GP) technology is proposed. By combining the front-end input buffers and the grouping technique into the time-interleaved architecture, the input capacitance effectively decreases and the available settling of input buffers increases. The proposed 16-channel time-interleaved SAR ADC achieves the performance of high-speed sampling rate and high input bandwidth. A zero-crossing detection technique is employed to correct timing skew among sub-ADCs. Gain and offset mismatches between sub-ADCs are calibrated in the digital domain. Asynchronous processing and monotonic capacitor switching technique used in the single-channel SAR ADC make the sub-ADC high speed and power-efficiency. Furthermore, AWCA technique solves the dynamic offset problem of the comparator in the sub-ADC. The measurement results show that ADC exhibits DNL of +0.17/-0.29 LSB and INL of +0.20/-0.18 LSB at 4 GS/s with Fin of 50 MHz. SNDR and SFDR are 32.15 dB and 41.04 dB at 4.5 GS/s with Fin of 1 GHz. The power consumption is 24.9 mW at 1.2 V supply voltage. As a result, the FoM (Power/2ENOB/FS) is 159 fJ/conversion-step. The whole chip including pads occupies 1.275 mm2 while area of core circuit is 0.195 mm2.