請用此 Handle URI 來引用此文件:
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/3828
完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 陳信樹(Hsin-Shu Chen) | |
dc.contributor.author | Wei-Chia Huang | en |
dc.contributor.author | 黃維家 | zh_TW |
dc.date.accessioned | 2021-05-13T08:37:14Z | - |
dc.date.available | 2019-08-15 | |
dc.date.available | 2021-05-13T08:37:14Z | - |
dc.date.copyright | 2016-09-08 | |
dc.date.issued | 2016 | |
dc.date.submitted | 2016-08-01 | |
dc.identifier.citation | [1] K. Okada et al., “A full 4-channel 6.3 Gb/s 60 GHz direct-conversion transceiver with low-power analog and digital baseband circuitry,” in IEEE Int. Solid-State Circuits Conf., Dig. Tech. Papers, Feb. 2012, pp. 218–220.
[2] T. Tsukizawa et al., “A fully integrated 60 GHz CMOS transceiver chipset based on WiGig/IEEE802.11ad with built-in self calibration for mobile applications,” in IEEE Int. Solid-State Circuits Conf., Dig. Tech. Papers, Feb. 2013, pp. 230–231. [3] S.-W.M. Chen and R.W. Brodersen, “A 6-bit 600-MS/s 5.3-mW asynchronous ADC in 0.13-μm CMOS,” IEEE J. Solid-State Circuits, vol. 41, no. 12, pp. 2669–2680, Dec. 2006. [4] J. Yang, T.L. Naing, and R.W. Brodersen, “A 1 GS/s 6 Bit 6.7 mW successive approximation ADC using asynchronous processing,” IEEE J. Solid-State Circuits, vol. 45, no. 8, pp. 1469–1478, Aug. 2010. [5] T. Jiang et al, “A single-channel, 1.25-GS/s, 6-bit, 6.08-mW asynchronous successive approximation ADC with improved feedback delay in 40-nm CMOS,” IEEE J. Solid-State Circuits, vol. 47, no. 10, pp. 2444–2453, Oct. 2012. [6] L. Kull et al, “A 3.1 mW 8b 1.2 GS/s single-channel asynchronous SAR ADC with alternate comparators for enhanced speed in 32 nm digital SOI CMOS,” IEEE J. Solid-State Circuits, vol. 48, no. 12, pp. 3049–3058, Dec. 2013. [7] E. Alpman et al., “A 1.1V 50mW 2.5GS/s 7b time-interleaved C-2C SAR ADC in 45nm LP digital CMOS,” in IEEE Int. Solid-State Circuits Conf., Dig. Tech. Papers, Feb. 2009, pp. 76–77. [8] P.J.A. Harpe et al., “A 0.47–1.6 mW 5-bit 0.5–1 GS/s time-interleaved SAR ADC for low-power UWB radios,” IEEE J. Solid-State Circuits, vol. 47, no. 7, pp. 1594–1602, Jul. 2012. [9] K. Doris et al., “A 480 mW 2.6 GS/s 10b time-interleaved ADC With 48.5 dB SNDR up to nyquist in 65 nm CMOS,” IEEE J. Solid-State Circuits, vol. 46, no. 12, pp. 2821–2833, Dec. 2011. [10] D. Stepanovic and B. Nikolic, “A 2.8 GS/s 44.6 mW time-interleaved ADC achieving 50.9 dB SNDR and 3 dB effective resolution bandwidth of 1.5 GHz in 65 nm CMOS,” IEEE J. Solid-State Circuits, vol. 48, no. 4, pp. 971–982, Apr. 2013. [11] N. Kurosawa et al., “Explicit analysis of channel mismatch effects in time-interleaved ADC systems” IEEE Trans. Circuits Syst.Ⅰ, Fundam. Theory Appl., vol.48, no.3, pp.261–271, Mar. 2001. [12] M. El-Chammas and B. Murmann, “A 12 GS/s 81-mW 5-bit time-in-terleaved flash ADC with background timing skew calibration,” IEEE J. Solid-State Circuits, vol. 46, no. 4, pp. 838–847, Apr. 2011. [13] C.-C. Huang, C.-Y. Wang, and J.-T. Wu, “A CMOS 6-bit 16-GS/s time-interleaved ADC using digital background calibration techniques,” IEEE J. Solid-State Circuits, vol. 46, no. 4, pp. 848–858, Apr. 2011. [14] S. Lee et al., “A 1 GS/s 10b 18.9 mW time-interleaved SAR ADC with background timing skew calibration,” IEEE J. Solid-State Circuits, vol. 49, no. 12, pp. 2846–2856, Dec. 2014. [15] N. Le Dortz et al., “A 1.62 GS/s time-interleaved SAR ADC with digital background mismatch calibration achieving interleaving spurs below 70 dBFS,” in IEEE Int. Solid-State Circuits Conf., Dig. Tech. Papers, Feb. 2014, pp. 386‒388. [16] C.-H. Tsai, “A single-channel 6-bit 800MS/s two-step SAR ADC”, Master Thesis, Graduate Institute of Electronics Engineering, College of Electrical Engineering & Computer Science, National Taiwan University, Nov. 2014. [17] I.-N. Ku et al., “A 40-mW 7-bit 2.2-GS/s time-interleaved subranging CMOS ADC for low-power gigabit wireless communications,” IEEE J. Solid-State Circuits, vol. 47, no. 8, pp. 1854–1865, Aug. 2012. [18] S.K. Gupta, M.A. Inerfield, and J. Wang, “A 1-GS/s 11-bit ADC with 55-dB SNDR, 250-mW power realized by a high bandwidth scalable time-interleaved architecture,” IEEE J. Solid-State Circuits, vol. 41, no. 12, pp. 2650–2657, Dec. 2006. [19] C.-C. Hsu et al., “An 11b 800MS/s time-interleaved ADC with digital background calibration,” in IEEE Int. Solid-State Circuits Conf., Dig. Tech. Papers, Feb. 2007, pp. 464–465. [20] S. Louwsma et al., “A 1.35 GS/s, 10 b, 175 mW time-interleaved AD converter in 0.13 μm CMOS,” IEEE J. Solid-State Circuits, vol. 43, no.4, pp. 778–786, Apr. 2008. [21] A. Varzaghani et al., “A 10.3-GS/s, 6-bit flash ADC for 10G ethernet applications,” IEEE J. Solid-State Circuits, vol. 48, no.12, pp. 3038–3048, Dec. 2013. [22] H. Wei et al., “An 8 bit 4GS/s120 mW CMOS ADC,” IEEE J. Solid-State Circuits, vol. 49, no.8, pp. 1751–1761, Aug. 2014. [23] Y. Duan and E. Alon, “A 12.8 GS/s time-interleaved ADC with 25 GHz effective resolution bandwidth and 4.6 ENOB,” IEEE J. Solid-State Circuits, vol. 49, no.8, pp. 1725–1738, Aug. 2014. [24] P. Schvan et al., “A 24GS/s 6b ADC in 90nm CMOS,” in IEEE Int. Solid-State Circuits Conf., Dig. Tech. Papers, Feb. 2008, pp. 544–545. [25] H.-Y. Tai et al., “A 6-bit 1-GS/s two-step SAR ADC in 40-nm CMOS,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 61, no. 5, pp.339–343, May 2014. [26] T.-Y. Tang, T.-H. Tsai and K. Chen et al., “Timing mismatch background calibration for time-interleaved ADCs,” in TENCON 2012 - 2012 IEEE Region 10 Conference, Nov. 2012, pp. 1–4. [27] B.P. Ginsburg et al., “500-MS/s 5-bit ADC in 65-nm CMOS with split capacitor array DAC,” IEEE J. Solid-State Circuits, vol. 42, no. 4, pp. 739–747, Apr. 2007. [28] Y. Zhu et al., “A 10-bit 100-MS/s reference-free SAR ADC in 90 nm CMOS,” IEEE J. Solid-State Circuits, vol.45, no.6, pp.1111–1121, Jun. 2010. [29] C.-C. Liu et al., “A 10-bit 50-MS/s SAR ADC with a monotonic capacitor switching procedure,” IEEE J. Solid-State Circuits, vol.45, no.4, pp.731–740, Apr. 2010. [30] B. Wicht, T. Nirschl, D. Schmitt-Landsiedel, “Yield and speed optimization of a latch-type voltage sense amplifier,” IEEE J. Solid-State Circuits, vol.39, no.7, pp.1148–1158, Jul. 2004. [31] S. Louwsma, E.V. Tuijl and B. Nauta, Time-interleaved analog-to-digital converters. New York: Springer, 2011, ch.2. [32] W. C. Black, JR., and D. A. Hodges, “Time interleaved converter arrays,” IEEE J. Solid-State Circuits, vol. SC-15, no.6, pp. 1022–1029, Dec. 1980. [33] K. Poulton, J.J. Corcoran, and T. Hornak. “A 1-GHz 6-bit ADC system,” IEEE J. Solid-State Circuits, vol. SC-22, no.6, pp. 962–970, Dec. 1987. [34] B.-R.-S. Sung et al., “A 6 bit 2 GS/s flash-assisted time-interleaved (FATI) SAR ADC with background offset calibration,” in Proc. IEEE Asian Solid-State Circuits Conf., 2013, pp. 281–284. [35] H. Lee et al., “A 6-bit 2.5-GS/s time-interleaved analog-to-digital converter using resistor-array sharing digital-to-analog converter,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., pp. 2371–2383, Nov. 2014. [36] S. Kundu et al., “A 1.2 V 2.64 GS/s 8 bit 39 mW skew-tolerant time-interleaved SAR ADC in 40 nm digital LP CMOS for 60 GHz WLAN,” IEEE Trans. Circuits Syst.Ⅰ, Reg. Papers, vol.62, no.8, pp.1929–1939, Aug. 2015. [37] R. Reeder and R. Ramachandran. “Wideband A/D converter front-end design considerations —When to use a double transformer configuration.” Analog Dialogue 40-3. pp. 19-22. 2006. [38] Mini-Circuits, “Surface mount RF transformer JTX-4-10T+,” http://www.minicircuits.com/pdfs/JTX-4-10T+.pdf [39] Mini-Circuits, “Surface mount RF transformer TCM4-14+,” http://www.minicircuits.com/pdfs/TCM4-14+.pdf [40] Mini-Circuits, “Surface mount RF transformer TCM4-452X+,” http://www.minicircuits.com/pdfs/TCM4-452X+.pdf [41] Tektronix, “11 GHz differential pulse splitter PSPL5320B datasheet,” http://www.tek.com/sites/tek.com/files/media/media/resources/PSPL5320B-Datasheet-0.pdf [42] C.-H. Chan et al., “A 6 b 5 GS/s 4 interleaved 3 b/cycle SAR ADC,” IEEE J. Solid-State Circuits, vol.51, no.2, pp.365–377, Feb. 2016. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/3828 | - |
dc.description.abstract | 在次世代無線通訊系統中,類比至數位轉換器必須操作在極高速的取樣頻率及低中解析度下。
本論文提出一個以40奈米CMOS一般製程,實現出六位元每秒四十五億次取樣的時間交錯連續漸進式類比至數位轉換器,藉由結合前端輸入緩衝器的架構及分組式技巧,有效地降低時間交錯式架構的輸入電容負載,並增加輸入訊號的可用安定時間,提出的16通道的時間交錯連續漸進式類比至數位轉換器得以達到高取樣速度及高輸入頻寬的表現。透過使用零交越 (zero-crossing) 偵測技巧,可以補償多通道間時間偏移的誤差,並透過數位校正處理多通道間的增益電壓及偏移電壓不匹配。在單通道方面,採用連續漸進式架構,並使用非同步處理及單向電容切換技巧使單通道具有高速度及高能量效率的特性。除此之外,任意選擇權重之電容陣列解決了單通道中比較器的動態偏移電壓的問題。 量測結果顯示,在每秒四十億的轉換,DNL和INL分別為+0.17/-0.29 LSB和+0.20/-0.18 LSB。在每秒四十五億的轉換及輸入頻率為一億赫茲下,SNDR和SFDR分別為32.15 dB和41.04 dB,在1.2 V的供應電壓下,功率消耗為24.9毫瓦,品質因數(FoM)為159 fJ/c.-s。全部的晶片面積大小為1.275 mm2,核心電路的面積是0.195平方毫米。 | zh_TW |
dc.description.abstract | Analog-to-digital converter (ADC) has to operate at ultra-high speed with low to medium resolution in the next-generation wireless communication systems.
A 6-bit 4.5 GS/s time-interleaved SAR ADC in 40 nm CMOS general–process (GP) technology is proposed. By combining the front-end input buffers and the grouping technique into the time-interleaved architecture, the input capacitance effectively decreases and the available settling of input buffers increases. The proposed 16-channel time-interleaved SAR ADC achieves the performance of high-speed sampling rate and high input bandwidth. A zero-crossing detection technique is employed to correct timing skew among sub-ADCs. Gain and offset mismatches between sub-ADCs are calibrated in the digital domain. Asynchronous processing and monotonic capacitor switching technique used in the single-channel SAR ADC make the sub-ADC high speed and power-efficiency. Furthermore, AWCA technique solves the dynamic offset problem of the comparator in the sub-ADC. The measurement results show that ADC exhibits DNL of +0.17/-0.29 LSB and INL of +0.20/-0.18 LSB at 4 GS/s with Fin of 50 MHz. SNDR and SFDR are 32.15 dB and 41.04 dB at 4.5 GS/s with Fin of 1 GHz. The power consumption is 24.9 mW at 1.2 V supply voltage. As a result, the FoM (Power/2ENOB/FS) is 159 fJ/conversion-step. The whole chip including pads occupies 1.275 mm2 while area of core circuit is 0.195 mm2. | en |
dc.description.provenance | Made available in DSpace on 2021-05-13T08:37:14Z (GMT). No. of bitstreams: 1 ntu-105-R02943026-1.pdf: 2853172 bytes, checksum: 57d342d48e1765b6d133585cf2b74658 (MD5) Previous issue date: 2016 | en |
dc.description.tableofcontents | 致謝 III
摘要 IV Abstract V Contents VI List of Figures X List of Tables XIV Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Thesis Organization 2 Chapter 2 Fundamentals of Analog to Digital Converter 4 2.1 Introduction 4 2.2 Performance Metrics 4 2.2.1 Static Performance 4 2.2.1.1 Offset and Gain Error 4 2.2.1.2 Differential and Integral Nonlinearities (DNL, and INL) 5 2.2.2 Dynamic Performance 6 2.2.2.1 Signal-to-Noise Ratio (SNR) 7 2.2.2.2 Total Harmonic Distortion (THD) 7 2.2.2.3 Spurious Free Dynamic Range (SFDR) 7 2.2.2.4 Signal-to-Noise and Distortion Ratio (SNDR) 8 2.2.2.5 Effective Number of Bits (ENOB) 8 2.2.2.6 Figure of Merit (FoM) 8 2.3 Architectures 9 2.3.1 Flash Architecture 9 2.3.2 Successive-Approximation-Register Architecture 10 2.3.1 Time-Interleaved Architecture 12 2.4 Error Sources and Calibrations in Time-Interleaved Architecture 14 2.4.1 Offset Mismatch and Calibration 14 2.4.2 Gain Mismatch and Calibration 17 2.4.1 Timing Skew Mismatch and Calibration 20 2.5 Summary 23 Chapter 3 Proposed Time-Interleaved SAR ADC 24 3.1 Introduction 24 3.2 Time-Interleaved ADC Architecture 24 3.2.1 One Rank Time-Interleaved Architecture 25 3.2.2 Two Rank Time-Interleaved Architecture 28 3.2.3 Grouping Technique 30 3.2.3.1 Prior Work 1: The 64-Channel Time-Interleaved 10-Bit SAR ADC [9] 32 3.2.3.2 Prior Work 2: The 4-Channel Time-Interleaved 6-Bit Flash ADC [21] 34 3.2.3.3 Prior Work 3: The 32-Channel Hierarchical Sampling Time-Interleaved 7-Bit SAR ADC [23] 36 3.3 Proposed Time-Interleaved SAR ADC 39 3.3.1 Design Considerations 44 3.3.1.1 Input Bandwidth and Settling Time Requirement 44 3.3.1.2 Offset and Gain Mismatch Calibration 50 3.3.1.3 Timing Skew Mismatch Calibration 51 3.3.1.4 Single-Channel SAR ADC 54 3.3.1.4.1 Asynchronous Processing 54 3.3.1.4.2 Monotonic Capacitor Switching 55 3.3.1.4.3 Dynamic Offset 56 3.3.1.4.4 Arbitrary Weight Capacitor Array (AWCA) Technique 57 3.3.1.4.5 Thermal Noise of AWCA 59 3.4 Summary 59 Chapter 4 Circuit Implementation and Simulation Results 61 4.1 Introduction 61 4.2 Building Blocks and Circuit Implementation 62 4.2.1 Front-End Circuit 62 4.2.2 Bias Circuit 65 4.2.3 Single-Channel SAR ADC 66 4.2.3.1 Sampling Switch 66 4.2.3.2 Arbitrary Weight Capacitor Array (AWCA) 68 4.2.3.3 Comparator 70 4.2.3.4 SAR Logic 72 4.2.3 Clock Generator 75 4.2.4 Delay Line 79 4.2.5 Clock Divider and Multiplexer 80 4.3 Overall ADC Simulation Results 82 4.4 Summary 85 Chapter 5 Measurement Results 86 5.1 Introduction 86 5.2 Floor Plan and Layout Design 86 5.3 PCB Design 89 5.4 Test Setup 94 5.5 Measurement Results 97 5.5.1 Static Performance 97 5.5.2 Dynamic Performance 99 5.6 Discussion 103 5.6.1 Dynamic performance with different RF transformers 103 5.6.2 Analysis of timing skew for simulation and measurement 107 5.7 Summary 113 Chapter 6 Conclusions 115 Chapter 7 Future Work 116 Bibliography 117 | |
dc.language.iso | en | |
dc.title | 一個高速採用時間交錯式的連續漸進式類比至數位轉換器 | zh_TW |
dc.title | A High-Speed Time-Interleaved SAR ADC | en |
dc.type | Thesis | |
dc.date.schoolyear | 104-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 劉深淵(Shen-Iuan Liu),蔡宗亨(Tsung-Heng Tsai),陳怡然(Yi-Jan Chen) | |
dc.subject.keyword | 類比至數位轉換器,時間交錯式,連續漸進式,分組技巧,高輸入頻寬, | zh_TW |
dc.subject.keyword | analog to digital converter,time-interleaved,SAR,grouping technique,high input bandwidth, | en |
dc.relation.page | 123 | |
dc.identifier.doi | 10.6342/NTU201601298 | |
dc.rights.note | 同意授權(全球公開) | |
dc.date.accepted | 2016-08-02 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
文件中的檔案:
檔案 | 大小 | 格式 | |
---|---|---|---|
ntu-105-1.pdf | 2.79 MB | Adobe PDF | 檢視/開啟 |
系統中的文件,除了特別指名其著作權條款之外,均受到著作權保護,並且保留所有的權利。