利用CMOS 0.13-μm製程並加入負阻架構之高增益放大器研製與良率分析

Abstract

在無線通訊蓬勃發展的年代，隨著技術的不斷提升，所需要的頻寬也越來越大。因此，向毫米波頻段發展是未來的趨勢。但是因為整合上的需求，雖然CMOS（金氧半互補式）製程在毫米波的表現不如GaAs（砷化鎵）等製程，不過因為IC整合上的需求，利用CMOS來研製射頻電路已經是不可避免的趨勢。 本論文的第一部份是利用0.13毫米CMOS製程來設計一個應用於V頻段的寬頻放大器。然後我們以第一顆放大器為基礎，加入了負阻概念，使其具有增益加強的效果，並驗證此方法是有效的。再來，我們利用一個設計失敗的多級串疊分佈式放大器來討論低頻震盪的產生原因與解決方法。 在本論文的第二個部份，我們試圖從匹配架構與匹配點來討論良率與它們之間的關係，並進一步討論在晶片中會影響良率的因素，並予以討論。

With the growing technique, wireless communication is more and more popular, and the desire of bandwidth is larger and larger. Therefore, the communication in MMW is approached. By the way, owing to the integration of chip, even if the performance of CMOS in MMW is worse than GaAs, we still try to use CMOS to design MMW front-end circuits. The first part of this thesis is using 0.13-um CMOS process to design a V-band broadband amplifier. Then we using this amplifier to be the core, and apply the negative resistance in to the circuit to make it have the gain-boosting effect. After measurement, we can verify this topology do works. Finally, we try to find out the reason of low frequency oscillation of a CMSDA ( Cascode Multi-Stage Distributed Amplifier ) and the way to solve this problem. The second part of this thesis, we try to verify the relationship between yield, matching topology, and matching point, and discuss the parameters which may effect the yield in chip.