具彈性邊界微結構之電彈性質研究

Abstract

本研究提出具非理想邊界、雜散電場、及殘餘應力之微結構吸附電壓解析模型，此模型成功的模擬實際的非線性機電耦合系統，並研發出一套適用於晶圓級檢測的全電信號的薄膜材料性質檢測方法，以檢測微結構之楊氏模數與殘留應力。以尤拉樑(Euler’s beam)模型以及最小能量法(minimum energy method)為理論基礎，推導出具初始應力之微橋狀樑在承受靜電負載下的吸附電壓的解析解，並可藉由量測兩組長度不同的微結構之吸附電壓，反算薄膜材料之楊氏模數與殘留應力。本研究以單晶矽、複晶矽、及濺鍍鋁作為測試結構材料，比較吸附電壓解析解與模擬、實驗數值的誤差，此三種不同測試結構吸附電壓誤差均在5%以內，在萃取薄膜材料機械性質方面，楊氏模數與殘留應力的誤差均在5%以內。本研究所提出之微結構的吸附電壓解析模型，其物理意義明確，可看出殘留應力、非理想邊界、雜散電場、及結構撓性等各物理量對吸附電壓的影響，因此可提供元件設計者作為設計參考指標，而所建立之全電性信號薄膜材料性質檢測技術，可利用現有之半導體量測設備，於晶圓製程線上進行即時的量測與監控，適合大量應用在半導體與微機電製程中。

This paper derives an approximate analytical solution to the pull-in voltage of micro bridge with non-ideal boundaries, fringing field capacitance and residual stresses. Besides, this paper also presents a novel and high-precision algorithm and method for extracting the Young’s modulus and residual stress of thin films through the pull-in voltage of micro test-key at wafer level. The approximate analytical solution is derived based on the Euler’s beam model and the minimum energy method. We derive a closed form solution for the pull-in voltages of micro fixed-fixed beam subjected to electrostatic loads and initial stress. Then one can use the aforesaid closed form solution of the pull-in voltage to extract the Young’s modulus and residual stress of the test structures. The test cases include single crystal silicone, poly-silicon, and sputtered aluminum. The accuracy of the present approximate analytical solution is verified through comparing with simulation results of commercial packages as well as experimental measured ones. The deviation of the present approximate analytical solution is within 5% for wide beam and narrow beam in small deflection regime. The deviation of the extracted Young’s modulus and residual stress are both within 5%. The present solution is fully analytical and highly accurate for device design. It can give us explicit physical meaning about how the residual stress, elastic boundary, structural flexibility, fringing field capacitance to affect pull-in voltage. The present method is expected to be applicable to the wafer-level testing in micro-device manufacture and compatible with the wafer-level testing in IC industry since the test and pick-up signals are both electrical.