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標題: | 低電壓互補式金氧半鎖相迴路與延遲迴路之設計與實作 Design and Implementation of Low Voltage CMOS Phase-Locked-Loop and Delay-Locked-Loop |
作者: | Chung-Ting Lu 呂宗庭 |
指導教授: | 呂良鴻 |
關鍵字: | 低電壓,低功率,鎖相迴路,延遲迴路, low voltage,low power,PLL,DLL,0.6 V, |
出版年 : | 2008 |
學位: | 碩士 |
摘要: | 近年來因為個人可攜帶式無線通訊系統的發展,低耗電的互補式金氧半電路設計吸引了很大的注意。低耗電的電路設計對於可攜帶式無線通訊非常重要,主要是因為功率決定了電池的壽命。另外,就算是家電產品,因為積體電路越做越密其功率的消耗也是菲常重要的課題。此外,對於通訊系統乾淨的時脈產生很重要。因此,本論文主要探討在低電壓的操作之下來製作產生時脈的鎖相迴路以及延遲迴路,並且儘可能的減少這些電路的功率消耗。
在第三章中,為了讓鎖相迴路可以操作在低電壓並且在消耗極低的功率之下可以在GHz的頻率維持很好的電路效能,在每個鎖相迴路的區塊中利用了FBB以及許多低電壓的電路設計技巧。利用0.18-μm 的製程,此電路操作在1.9 GHz 的頻帶,並且在0.5 伏特的供應電壓之下,消耗了4.5 mW。本鎖相迴路的相位雜訊約為-83.4 dBc/Hz @100- kHz 以及-135.3 dBc/Hz @ 10-MHz offset。 第四章介紹改良式的四相位壓控震盪器。此架構可以在維持不錯的相位雜訊以及相位誤差之下減少功率的消耗,以達到低電壓低功率的要求。Push-push 乘頻器用來產生雙頻的信號。另外,利用第二章所介紹的低電壓電路技巧將此四相位的壓控震盪器應用在此2.4GHz 的鎖相迴路。此電路的量測結果的相位雜訊為-113.05 dBc/Hz @1-MHz offset,相位誤差約為0.6°。另外,此電路在0.5 伏特的供應電壓之下消耗了12 mW 的功率。 在第五張介紹另一個迴路:低電壓低功率低時基誤差且寬頻之延遲迴路。除了繼續利用第二章的低電壓電路技巧之外,也提出了一個壓控延遲電路來增進其之線性度以及增加頻率範圍以及減少時基誤差。模擬結果指出此提出的延遲回路的架構可以操作在100~400MHz 的頻帶,所造成的時基誤差在100MHz 是25 ps 在400MHz 是13 ps。另外,此電路在0.6 伏特之下的供應電壓之下,根據不一樣的頻帶銷耗了2~4 mW。 Low-power CMOS designs have attracted great attention in the past few years. For portable wireless communication systems such as mobile phones, the power dissipation of the integrated circuits is of crucial importance as it predetermines the battery life. Even for electronic products operated at household electricity, the power consumption and the associated thermal problems are still essential design issues as the packing density of a fully integrated system increases. Besides, clocks are very important in the above mentioned portable devices. Therefore, this thesis is devoted to the implementation of clock production such as phase-locked-loops and delay-locked-loops operated at low voltage with low power consumption. In chapter 3, by employing the forward-body-bias (FBB) technique and low-voltage circuit topologies for the individual building blocks, a phase-locked loop (PLL) is proposed to operate at reduced supply voltage and power consumption while maintaining the desirable circuit performance at multi-gigahertz frequencies. Using a standard 0.18-μm CMOS process, a 1.9-GHz PLL is implemented for demonstration. Consuming a dc power of 4.5 mW from a 0.5-V supply voltage, the fabricated circuit exhibits in-band and out-of-band phase noise of -83.4 dBc/Hz and -135.3 dBc/Hz at 100- kHz and 10-MHz frequency offset, respectively, and a side-band spur with a power level 44 dB below the carrier. A ring-like LC QVCO technique is proposed in chapter 4. The proposed QVCO can achieve desirable phase noise and phase error performance with much less power consumption. Push-push frequency doubler technique is also used to produce the dual band signals. This QVCO is then applied in a PLL. The forward-body-bias technique and low-voltage circuit topologies described in Chapter 2 for the individual building blocks are utilized in a phase-locked loop (PLL) at reduced supply voltage and power consumption while maintaining the desirable circuit performance at multi-gigahertz frequencies. Using a standard 0.18-μm CMOS process, a 2.4-GHz PLL is implemented for demonstration. Consuming a dc power of 12 mW from a 0.5-V supply voltage, the fabricated circuit exhibits quadrature outputs with phase noise -113.05 dBc/Hz at 1-MHz frequency offset, and a side-band spur with a power level 38 dB below the carrier. Besides, the phase error is around 0.6° and the IRR is 38dB. A low voltage, low power, low jitter, and wide range delay-locked-loop (DLL) is proposed in chapter 5. In this design low voltage circuits design approaches and the proposed voltage control delay line (VCDL) have been used to attain the above mentioned performance. Besides, problems in the conventional circuits such as linearity are solved by this new skill. In this way the delay range can cover all the control voltage. Fabricated in a standard 0.18-μm CMOS process, the simulation results show that under the supply voltage of 0.6 V, the proposed DLL can operate from 100 to 400 MHz, and the current drawn from the supply is 4 mA and 7.5 mA, separately. With the data simulated in HSPICE, the corresponding jitter simulated in the MATLAB is 25 ps to 13 ps. The DLL occupies a total area of 680 μm × 680 μm. |
URI: | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/26996 |
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顯示於系所單位: | 電子工程學研究所 |
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