請用此 Handle URI 來引用此文件:
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/26996
完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 呂良鴻 | |
dc.contributor.author | Chung-Ting Lu | en |
dc.contributor.author | 呂宗庭 | zh_TW |
dc.date.accessioned | 2021-06-12T17:53:32Z | - |
dc.date.available | 2011-04-15 | |
dc.date.copyright | 2008-04-15 | |
dc.date.issued | 2008 | |
dc.date.submitted | 2008-03-07 | |
dc.identifier.citation | [1] J. Rabaey and et al., “PicoRadios for wireless sensor networks: the next challenge in ultra-low power design,” IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, pp. 200-201, Feb. 2002.
[2] P. Choi and et al., “An experimental coin-sized radio for extremely low power WPAN (IEEE 802.15.4) application at 2.4 GHz,” IEEE J. Solid-State Circuits, vol. 38, no. 12, pp. 2258-2268, Dec. 2003. [3] I. Nam and et al., “A 2.4-GHz low-power low-IF receiver and direct- conversion transmitter in 0.18-µm CMOS for IEEE 802.15.4 WPAN applications,” IEEE Trans. Microw. Theory Tech., vol. 55, no. 4, pp. 682-689, April 2007. [4] T.-K. Nguyen and et al., “A low-power CMOS direct conversion receiver with 3-dB NF and 30-kHz flicker-noise corner for 915-MHz band IEEE 802.15.4 ZigBee standard,” IEEE Trans. Microw. Theory Tech., vol. 54, no. 2, part 1, pp. 735-741, Feb. 2006. [5] N. Stanic, P. Kinget and Y. Tsividis, “A 0.5 V 900 MHz CMOS receiver front end,” IEEE Symposium on VLSI Circuits Digest of Technical Papers, pp. 228-229, June 2006. [6] M. N. El-Gamal and et al., “Very low-voltage (0.8 V) CMOS receiver frontend for 5GHz RF applications,” Circuits, Devices and Systems, IEE Proceedings, vol. 149, no. 5/6, pp.355-362, Oct.-Dec. 2002. [7] A.-S. Porret and et al., “A low-power low-voltage transceiver architecture suitable for wireless distributed sensors network,” IEEE Int. Symp. on Circuits and Systems, vol. 1, pp. 56-59, May 2000. [8] M. Harada and et al., “2-GHz RF front-end circuits in CMOS/SIMOX operating at an extremely low voltage of 0.5 V,” IEEE J. Solid-State Circuits, vol. 35, no. 12, pp. 2000-2004, Dec. 2000. [9] International Technology Roadmap for Semiconductors, Semiconductor Industry Association (2004). [Online]. Available: http://public.itrs.net/ [10] J. B. Kuo and J.-H. Lou, Low-voltage CMOS VLSI circuits. New York: John Wiley & Sons, 1999. [11] Woogeun Rhee, “Design of high performance CMOS charge pumps in phase-locked loops,” IEEE ISCAS’99, vol. 2, pp. 545-548, May. 1999 [12] I. Shahriary et al., “GaAs monolithic phase/frequency discriminator,” IEEE GaAs IC Symp. Dig. Of Tech. Papers, pp. 183-186, 1985 [13] H.-H. Hsieh and L.-H. Lu, “A high-performance CMOS voltage-controlled oscillator for ultra-low-voltage operations,” Microwave Theory and Techniques, IEEE Transactions on, vol. 55, pp. 467-473, Mar. 2007 [14] Swaminathan, Ashok, Wang, Kevin J, and Galton, Ian, “A Wide-Bandwidth 2.4GHz ISM-Band Fractional-N PLL with Adaptive Phase-Noise Cancellation,” Solid-State Circuits Conference, 2007. ISSCC sec. 17.1 Feb. 2007. [15] Sangho Shin, Kwyro Lee, and Sungo-Mo Kang, “4.2mW CMOS Frequency Synthesizer for 2.4GHz ZigBee Application with Fast Settling Time Performance,” Microwave Symposium Digest, 2006. IEEE MTT-S International, pp. 411-414, June 2006 [16] J. Rabaey and et al., “PicoRadios for wireless sensor networks: the next challenge in ultra-low power design,” IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, pp. 200-201, Feb. 2002. [17] P. Choi and et al., “An experimental coin-sized radio for extremely low power WPAN (IEEE 802.15.4) application at 2.4 GHz,” IEEE J. Solid-State Circuits, vol. 38, no. 12, pp. 2258-2268, Dec. 2003. [18] A. Rofougaran, J. Rael, M. Rofougaran, and A. Abidi, “A 900 MHz CMOS LC-oscillator with quadrature outputs,” in Proc. ISSCC 1996, Feb. 1996, pp. 392-393. [19] Pietro Andreani, Andrea Bonfanti, Luca Romano, and Carlo Samori, “Analysis and Design of a 1.8-GHz CMOS LC Quadrature VCO,” IEEE J. Solid-State Circuits, vol. 37, no. 12, pp. 1737-1474, Dec. 2002 [20] P. Andreani, “A low-phase-noise, low-phase-error 1.8 GHz quadrature CMOS VCO,” in Proc. ISSCC 2002, Feb. 2002, pp. 290-291. [21] Donghyun Baek, Jeonggeun Kim, and Songcheol Hong, “A Dual-Band (13/22-GHz) VCO Based on Resonant Mode Switching,” IEEE Microwave And Wireless Components Letters, vol. 13, no. 10, Oct 2003. [22] S.-M. Yim and K. K. O, “Demonstration of a switched resonator concept in a dual-band monolithic CMOS LC-tuned VCO,” in Proc. IEEE Custom Integrated Circuits Conf., pp. 205-208, May 2001 [23] Hyunchol Shin, Zhiwei Xu, and M. Frank Chang, “A 1.8-V 6/9-GHz Reconfigurable Dual-Band Quadrature LC VCO in SiGe BiCMOS Technology,” IEEE J. Solid-State Circuits, vol. 38, no. 6, pp. 1028-1032, Jun. 2003 [24] Seong-Mo Yim and Kenneth K. O, “ Switched Resonators and Their Applications in a Dual-Band Monolithic CMOS LC-tuned VCO,” IEEE Transactions on Microwave Theory and Techniques, vol. 54, no. 1, pp. 74-81, Jan 2006. [25] H.-H. Hsieh and L.-H. Lu, “A high-performance CMOS voltage-controlled oscillator for ultra-low-voltage operations,” Microwave Theory and Techniques, IEEE Transactions on, vol. 55, pp. 467-473, Mar. 2007 [26] I. Shahriary et al., “GaAs monolithic phase/frequency discriminator,” IEEE GaAs IC Symp. Dig. Of Tech. Papers, pp. 183-186, 1985 [27] Woogeun Rhee, “Design of high performance CMOS charge pumps in phase-locked loops,” IEEE ISCAS’99, vol. 2, pp. 545-548, May. 1999 [28] Zhinian Shu, Ka Lok Lee, and Bosco H. Leung, “A 2.4-GHz Ring-Oscillator-Based CMOS Frequency Synthesizer With a Fractional Divider Dual-PLL Architecture,” IEEE J. Solid-State Circuits, vol. 39, no. 3, pp. 452-462, Mar. 2004 [29] Sangho Shin, Kwyro Lee, and Sung-Mo Kang, “Low-power 2.4GHz CMOS frequency synthesizer with differentially controlled MOS varactors,” Circuits and Systems, 2006. ISCAS 2006. pp. 553-556, May 2006 [30] R. B Watson, Jr. and R. B. Iknaian, “Clock buffer chip with multiple target automatic skew compensations,” IEEE J. Solid-State Circuits, vol. 30, pp. 1267-1276, Nov. 1995. [31] Y. Moon, J. Choi, K. Lee, D. K. Jeong, and M. K. Kim, “An all-analog multiphase delay-locked loop using a replica delay line for wide-range operation and low-jitter performance, IEEE J. Solid-State Circuits, vol. 35, pp. 377-384, Mar. 2000. [32] Hsiang-Hui Chang, Jyh-Woei Lin, Ching-Yuan Yang, and Shen-Iuan Liu, “A Wide-Range Delay-Locked Loop With a Fixed Latency of One Clock Cycle,” IEEE J. Solid-State Circuits, vol. 37, pp. 1021-1027, Aug. 2002 [33] S. Pellerano, S. Levantino, C. Samori, and A. L. Lacaita, “A 13.5-mW 5-GHz Frequency Synthesizer With Dynamic-Logic Frequency Divider, IEEE J. Solid-State Circuits, vol. 39, pp. 378-383, Feb. 2004. [34] Sang-O Jeon, Tae-Sik Cheung and Woo-Young Choi, “ Phase/ Frequency detectors for high-speed PLL applications,” Electronic letters, vol. 34, no. 22, pp. 2120-2121, Oct. 1998. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/26996 | - |
dc.description.abstract | 近年來因為個人可攜帶式無線通訊系統的發展,低耗電的互補式金氧半電路設計吸引了很大的注意。低耗電的電路設計對於可攜帶式無線通訊非常重要,主要是因為功率決定了電池的壽命。另外,就算是家電產品,因為積體電路越做越密其功率的消耗也是菲常重要的課題。此外,對於通訊系統乾淨的時脈產生很重要。因此,本論文主要探討在低電壓的操作之下來製作產生時脈的鎖相迴路以及延遲迴路,並且儘可能的減少這些電路的功率消耗。
在第三章中,為了讓鎖相迴路可以操作在低電壓並且在消耗極低的功率之下可以在GHz的頻率維持很好的電路效能,在每個鎖相迴路的區塊中利用了FBB以及許多低電壓的電路設計技巧。利用0.18-μm 的製程,此電路操作在1.9 GHz 的頻帶,並且在0.5 伏特的供應電壓之下,消耗了4.5 mW。本鎖相迴路的相位雜訊約為-83.4 dBc/Hz @100- kHz 以及-135.3 dBc/Hz @ 10-MHz offset。 第四章介紹改良式的四相位壓控震盪器。此架構可以在維持不錯的相位雜訊以及相位誤差之下減少功率的消耗,以達到低電壓低功率的要求。Push-push 乘頻器用來產生雙頻的信號。另外,利用第二章所介紹的低電壓電路技巧將此四相位的壓控震盪器應用在此2.4GHz 的鎖相迴路。此電路的量測結果的相位雜訊為-113.05 dBc/Hz @1-MHz offset,相位誤差約為0.6°。另外,此電路在0.5 伏特的供應電壓之下消耗了12 mW 的功率。 在第五張介紹另一個迴路:低電壓低功率低時基誤差且寬頻之延遲迴路。除了繼續利用第二章的低電壓電路技巧之外,也提出了一個壓控延遲電路來增進其之線性度以及增加頻率範圍以及減少時基誤差。模擬結果指出此提出的延遲回路的架構可以操作在100~400MHz 的頻帶,所造成的時基誤差在100MHz 是25 ps 在400MHz 是13 ps。另外,此電路在0.6 伏特之下的供應電壓之下,根據不一樣的頻帶銷耗了2~4 mW。 | zh_TW |
dc.description.abstract | Low-power CMOS designs have attracted great attention in the past few years. For portable wireless communication systems such as mobile phones, the power dissipation of the integrated circuits is of crucial importance as it predetermines the battery life. Even for electronic products operated at household electricity, the power consumption and the associated thermal problems are still essential design issues as the packing density of a fully integrated system increases. Besides, clocks are very important in the above mentioned portable devices. Therefore, this thesis is devoted to the implementation of clock production such as phase-locked-loops and delay-locked-loops operated at low voltage with low power consumption.
In chapter 3, by employing the forward-body-bias (FBB) technique and low-voltage circuit topologies for the individual building blocks, a phase-locked loop (PLL) is proposed to operate at reduced supply voltage and power consumption while maintaining the desirable circuit performance at multi-gigahertz frequencies. Using a standard 0.18-μm CMOS process, a 1.9-GHz PLL is implemented for demonstration. Consuming a dc power of 4.5 mW from a 0.5-V supply voltage, the fabricated circuit exhibits in-band and out-of-band phase noise of -83.4 dBc/Hz and -135.3 dBc/Hz at 100- kHz and 10-MHz frequency offset, respectively, and a side-band spur with a power level 44 dB below the carrier. A ring-like LC QVCO technique is proposed in chapter 4. The proposed QVCO can achieve desirable phase noise and phase error performance with much less power consumption. Push-push frequency doubler technique is also used to produce the dual band signals. This QVCO is then applied in a PLL. The forward-body-bias technique and low-voltage circuit topologies described in Chapter 2 for the individual building blocks are utilized in a phase-locked loop (PLL) at reduced supply voltage and power consumption while maintaining the desirable circuit performance at multi-gigahertz frequencies. Using a standard 0.18-μm CMOS process, a 2.4-GHz PLL is implemented for demonstration. Consuming a dc power of 12 mW from a 0.5-V supply voltage, the fabricated circuit exhibits quadrature outputs with phase noise -113.05 dBc/Hz at 1-MHz frequency offset, and a side-band spur with a power level 38 dB below the carrier. Besides, the phase error is around 0.6° and the IRR is 38dB. A low voltage, low power, low jitter, and wide range delay-locked-loop (DLL) is proposed in chapter 5. In this design low voltage circuits design approaches and the proposed voltage control delay line (VCDL) have been used to attain the above mentioned performance. Besides, problems in the conventional circuits such as linearity are solved by this new skill. In this way the delay range can cover all the control voltage. Fabricated in a standard 0.18-μm CMOS process, the simulation results show that under the supply voltage of 0.6 V, the proposed DLL can operate from 100 to 400 MHz, and the current drawn from the supply is 4 mA and 7.5 mA, separately. With the data simulated in HSPICE, the corresponding jitter simulated in the MATLAB is 25 ps to 13 ps. The DLL occupies a total area of 680 μm × 680 μm. | en |
dc.description.provenance | Made available in DSpace on 2021-06-12T17:53:32Z (GMT). No. of bitstreams: 1 ntu-97-R94943023-1.pdf: 3459129 bytes, checksum: 1929e351c90baf087ebd53039de94825 (MD5) Previous issue date: 2008 | en |
dc.description.tableofcontents | Acknowledgments V
Abstracts VII Table of Contents X List of Figures XIII List of Tables XVII Chapter1 Introduction 1 1.1 Motivation 1 1.2 Overview of the thesis 1 Chapter2 Background of PLL and FBB 3 2.1 Introduction to Building Blocks of PLL 3 2.1.1 Phase Frequency Detector (PFD) 4 2.1.2 Charge pump 6 2.1.3 Voltage controlled oscillator 7 2.1.4 Frequency divider 7 2.1.5 Low pass filter(LPF) 8 2.2 General considerations 8 2.2.1 Phase noise and side band spurs 8 2.2.2 Tracking and acquisition 11 2.3 System and Noise Analysis 11 2.3.1 System analysis 12 2.3.2 Phase noise analysis at input 13 2.3.3 Phase Noise of VCO 14 2.4 Low Voltage Consideration 14 2.4.1 Forward-body-biasing technique 14 2.4.2 Other issues 15 Chapter 3 A low voltage 1.9-GHz CMOS PLL 17 3.1 Introduction 17 3.2 Architecture of Phase-Locked-Loop 18 3.3 Circuit Implementation 19 3.3.1 Proposed De-mismatched Current Charge Pump 19 3.3.2 Phase Frequency Detector 22 3.3.3 VCO and Frequency Divider 23 3.4 Experimental Results 26 3.5 Conclusion 29 Chapter 4 A Low-Voltage 2.4-GHz Quadrature PLL 30 4.1 Introduction 30 4.2 The Proposed QVCO and Dual Band VCO Topology 31 4.2.1 The proposed QVCO topology 31 4.2.2 The dual band VCO 37 4.2.3 VCO topology 38 4.3 The Low Voltage Quadrature Dual Band PLL 39 4.4 Experimental Results 42 4.5 Conclusion 45 Chapter 5 A Low Voltage, Low Jitter, and Wide Range DLL 46 5.1 Introduction 46 5.2 The Proposed VCDL and Its Application to DLL 48 5.2.1 The DLL architecture 48 5.2.2 The proposed voltage controlled delay line(VCDL) 49 5.3 Circuits Design of DLL 52 5.3.1 Start-controlled Circuits 52 5.3.2 Phase Frequency Detector 52 5.3.3 Charge pump 53 5.3.4 The proposed VCDL 54 5.4 Simulation Results 54 5.5 Conclusion 59 Chapter 6 Conclusion 60 Reference: 61 | |
dc.language.iso | en | |
dc.title | 低電壓互補式金氧半鎖相迴路與延遲迴路之設計與實作 | zh_TW |
dc.title | Design and Implementation of Low Voltage CMOS Phase-Locked-Loop and Delay-Locked-Loop | en |
dc.type | Thesis | |
dc.date.schoolyear | 96-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 黃俊郎,鄭裕庭,闕河鳴 | |
dc.subject.keyword | 低電壓,低功率,鎖相迴路,延遲迴路, | zh_TW |
dc.subject.keyword | low voltage,low power,PLL,DLL,0.6 V, | en |
dc.relation.page | 62 | |
dc.rights.note | 有償授權 | |
dc.date.accepted | 2008-03-07 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
文件中的檔案:
檔案 | 大小 | 格式 | |
---|---|---|---|
ntu-97-1.pdf 目前未授權公開取用 | 3.38 MB | Adobe PDF |
系統中的文件,除了特別指名其著作權條款之外,均受到著作權保護,並且保留所有的權利。