Skip navigation

DSpace JSPUI

DSpace preserves and enables easy and open access to all types of digital content including text, images, moving images, mpegs and data sets

Learn More
DSpace logo
English
中文
  • Browse
    • Communities
      & Collections
    • Publication Year
    • Author
    • Title
    • Subject
  • Search TDR
  • Rights Q&A
    • My Page
    • Receive email
      updates
    • Edit Profile
  1. NTU Theses and Dissertations Repository
  2. 電機資訊學院
  3. 電子工程學研究所
Please use this identifier to cite or link to this item: http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/26623
Title: 應用於光通訊之時脈產生器與突發式時脈資料回復電路
Clock Generator and Burst-Mode CDR for Optical Communications
Authors: Lan-Chou Cho
卓聯洲
Advisor: 劉深淵(Shen-Iuan Liu)
Keyword: 鎖相迴路:多相位:資料回復電路:除法器,
PLL:Multi-phase:CDR:divider,
Publication Year : 2008
Degree: 博士
Abstract: 隨著科技的發展與進步,需要越來越大的資料傳輸量,高速長距離通訊系統,幾乎都採用光纖通訊技術來達到廣泛的應用,其中,發射器中的時脈產生器與接收器中的時脈資料回復電路,皆在光纖通訊系統扮演關鍵性角色。
在此篇論文,首先,介紹一應用於光纖通訊的38GHz 0.13um CMOS時脈產生器,它採用八相位電感電容壓控振盪器(8-phase LC VCO),可以產生八個相位,高達38GHz輸出頻率的時脈訊號,論文中將會推導出,使用電容電感串接高通式架構,可以維持較高的頻率,並採用分布負載式除頻器(split-load frequency divider),可以有效的增加除頻器的操作頻率,最後採用能降低相位誤差的相位偵測器(phase detector),可以改善輸出的邊頻(frequency spur)。
第二,說明一應用於被動光纖網路(PON)通訊的34Gb/s 90nm CMOS 突發式時脈資料回復電路(burst mode CDR)。為了符合被動光纖網路多工控制的應用,它需要非常短的鎖定時間,為了減少依賴輸入資料產生的抖動(data dependent jitter),並且產生高速的時脈,採用了電感電容閘式壓控振盪器(LC Gated VCO),為了要接收寬頻的資料,採用一個寬頻輸入匹配電路以及一個寬頻資料緩衝器,最後採用相位選擇器,來預防因全速率(full-rate)操作下,可能產生的錯誤鎖定。
最後,除了完成以上光纖通訊關鍵電路,我們也提出一些可應用於未來的高速除頻器,高速除頻器一般採用注入鎖定式除頻器,因為可以產生最高的操作頻率以及較低的能量消耗。三種注入鎖定式除頻器,分別可以操作在72-78 GHz, 82.7-85.8GHz以及93.5~109.4GHz的範圍,論文中將會推導出,不同的架構,將會影響最高可操作的頻率以及可除頻範圍。
With the development and advancement of technology, the more and more data transmission quantity is needed. High-speed and long-distance communication systems mostly adopt the optical networks in various applications. The clock generator for transmitter and the clock data recovery (CDR) for receiver play the critical roles.
First, a 38GHz clock generator in 0.13um CMOS is presented for optical communications. An 8-phase LC voltage-controlled oscillator is presented to generate the 8-phase 38GHz outputs. The highpass characteristic CL ladder topology sustains the high-frequency signals will be derived in this dissertation. The split-load divider is presented to extend the operation frequency. The phase detector (PD) improves the static phase error and improves the frequency spur.
Second, a 34Gb/s burse-mode CDR in 90nm CMOS is presented for passive optical network (PON) communications. The PON is attracting in the point-to-multipoint communication systems. It needs very short settling time. To reduce the data jitter and generate the high-frequency output clock, the LC gated voltage-controlled oscillator is presented. To receive and transmit the broadband data, a wideband input matching circuit and a wideband data buffer are presented, respectively. The phase selector is proposed to overcome the false phase lock due to the full-rate operation.
Finally, in addition to realize the above key components of optical communications, some high speed frequency divider is presented for future applications. The injection-locked frequency divider (ILFD) is attractive because the highest operation frequency and low power consumption. Three ILFDs have the locking range of 72-78 GHz, 82.7-85.8GHz and 93.5~109.4GHz, respectively. It will derive the center frequency and the locking range for different ILFDs.
URI: http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/26623
Fulltext Rights: 未授權
Appears in Collections:電子工程學研究所

Files in This Item:
File SizeFormat 
ntu-97-1.pdf
  Restricted Access
6.97 MBAdobe PDF
Show full item record


Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.

社群連結
聯絡資訊
10617臺北市大安區羅斯福路四段1號
No.1 Sec.4, Roosevelt Rd., Taipei, Taiwan, R.O.C. 106
Tel: (02)33662353
Email: ntuetds@ntu.edu.tw
意見箱
相關連結
館藏目錄
國內圖書館整合查詢 MetaCat
臺大學術典藏 NTU Scholars
臺大圖書館數位典藏館
本站聲明
© NTU Library All Rights Reserved