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  1. NTU Theses and Dissertations Repository
  2. 電機資訊學院
  3. 電子工程學研究所
請用此 Handle URI 來引用此文件: http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/26623
完整後設資料紀錄
DC 欄位值語言
dc.contributor.advisor劉深淵(Shen-Iuan Liu)
dc.contributor.authorLan-Chou Choen
dc.contributor.author卓聯洲zh_TW
dc.date.accessioned2021-06-08T07:17:57Z-
dc.date.copyright2008-07-30
dc.date.issued2008
dc.date.submitted2008-07-25
dc.identifier.citation[1] http://en.wikipedia.org/wiki/Synchronous_optical_networking
[2] http://www.ieee802.org/3/10GEPON_study
[3] B. Stilling, “Bit rate and protocol independent clock and data recovery,” Electronics Letters, vol. 36, pp. 824-825, April. 2000.
[4] C. R. Hogge, “A Self-Correcting Clock Recovery Circuit,” IEEE J. Lightwave Tech, vol. 3, pp. 1312-1314, Dec. 1985.
[5] J. D. H. Alexander, “Clock Recovery from Random Binary Data,” Electronics Letters, vol. 11, pp. 541-542, Oct. 1975.
[6] X. Guan, H. Hashemi, and A. Hajimiri, “A fully integrated 24-GHz eight-element phased-array receiver in silicon,” IEEE J. Solid-State Circuits, vol. 39, pp. 2311-2320, Dec. 2004.
[7] H. Tao, D.K. Shaeffer, M. Xu, S. Benyamin, V. Condito, S. Kudszus, Q. Lee; A. Ong, A. Shahani, Si. Xiaomin, W. Wong, and M. Tarsia, “40-43-Gb/s OC-768 16:1 MUX/CMU chipset with SFI-5 compliance,” IEEE J. Solid-State Circuits, vol. 38, pp. 2169-2180, Dec. 2003.
[8] C. Lee, L. C. Chou, S. I. Liu, C. L. Ko, Y. Z. Juang and C. F. Chiu, “A 1.2V 37-38.5GHz 8-phase clock generator in 0.13um CMOS technology,” in Symposium on VLSI Circuits, Dig. Tech. Papers, pp. 27-28, June 2006.
[9] J. J. Kim and B. Kim, “A low-phase-noise CMOS LC oscillator with a ring structure,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, pp. 430-431, Feb. 2000.
[10] J. Lee and B. Razavi, “A 40-Gb/s clock and data recovery circuit in 0.18um CMOS technology,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, pp. 242-243, Feb. 2003.
[11] W. L. Chan, H. Veenstra, and J. R. Long, “A 32GHz quadrature LC-VCO in 0.25um SiGe BiCMOS technology,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, pp. 538-539, Feb. 2005.
[12] B. Razavi, “CMOS transceivers for 60GHz band”, in IEEE RF IC Symposium Dig. Tech. Papers, pp. 231-234, June 2006.
[13] J. Lee and S. Wu, “Design and analysis of a 20-GHz clock multiplication unit in 0.18um CMOS technology,” in Symposium on VLSI Circuits, Dig. Tech. Papers, pp. 140-143, June 2005.
[14] R. C. H. van de Beek, C. S. Vaucher, D. M. W. Leenaerts, E. A. M. Klumperink, and B. Nauta, “A 2.5-10-GHz clock multiplier unit with 0.22-ps RMS jitter in standard 0.18um CMOS,” IEEE J. Solid-State Circuits, vol. 39, pp. 1862-1872, Nov. 2004.
[15] H. Knapp, H. D. Wohlmuth, M. Wurzer, and M. Rest, “25GHz static frequency divider and 25G/s multiplexer in 0.12um CMOS,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2002, pp. 302-303.
[16] A. Rylyakov and T. Zwick, “96-GHz static frequency divider in SiGe bipolar technology,” IEEE J. Solid-State Circuits, vol. 39, pp. 1712-1715, Oct. 2004.
[17] T. Otsuji, M. Yoneyama, K. Murata, and E. Sano, “A super-dynamic flip-flop circuit for broadband application up to 24Gbit/s utilizing production-level 0.2um GaAs MESFETs,” IEEE J. Solid-State Circuits, vol. 32, pp. 1357-1362, Sept. 1997.
[18] R. E. Best, Phase-Locked Loop, New York: McGraw Hill, 2003.
[19] J. Kim et al., ” A 20-GHz phase-locked loop for 40Gb/s serializing transmitter in 0.13um CMOS,” in Dig.2005 Symposium on VLSI Circuits, pp. 144-147, June 2005.
[20] J. Lee, ” High-speed circuit designs for transmitters in broadband data links” IEEE J. Solid-State Circuits, vol. 41, pp. 1004-1015, May 2006.
[21] J. Jeong, and Y. Kwon, “A fully integrated V-Band PLL MMIC using 0.15-um GaAs pHEMT technology” IEEE J. Solid-State Circuits, vol. 41, pp. 1042-1050, May 2006.
[22] M. Kamata, T. Shono, T. Saba, I. Sasase, and S. Mori, ”Third-order phase-locked loops using dual loops with improved stability” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Aug. 1997, pp. 338-341.
[23] D. Messerschmitt, “Frequency detectors for PLL acquisition in timing and carrier recovery” IEEE Transactions on Communications, vol. 27, pp. 1288–1295, Sept. 1979.
[24] I. V. Thompson, and P. V. Brennan, “Fourth-order PLL loop filter design technique with invariant natural frequency and phase margin,” IEE Circuits, Devices and Systems, Proceedings, vol. 152, pp. 103-108, April 2005.
[25] M. Kamata, T. Shono, T. Saba, I. Sasase, and S. Mori, “Third-order phase-locked loops using dual loops with improved stability,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Aug. 1997, pp. 338-341.
[26] A. Mehrotra, “Noise analysis of phase-locked loops,” IEEE Transactions on Circuits and Systems, vol. 49, pp. 1309-1316, Sept. 2002.
[27] J. Lee, K. S. Kundert, and B. Razavi, “Analysis and modeling of bang-bang clock and data recovery circuits,” IEEE J. Solid-State Circuits, vol. 39, pp. 1571-1580 Sept. 2004.
[28] C. Cao, Y. Ding, and K. K. O, “A 50-GHz phase-locked loop in 130-nm CMOS,” IEEE Custom Integrated Circuits Conference, pp. 21-24, Sept. 2006.
[29] M. Banu and A. E. Dunlop, “A 660Mb/s CMOS clock recovery circuit with instantaneous locking for NRZ data and burst-mode transmission” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, pp. 102-103, Feb. 1993.
[30] A. E. Dunlop, W. C. Fischer, M. Banu, T. Gabara, “150/30 Mb/s CMOS non-oversampled clock and data recovery circuits with instantaneous locking and jitter rejection” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, pp. 44-45, Feb. 1995.
[31] M. Nakamura, N. Ishihara, and Y. Akazawa, “A 156 Mbps CMOS clock recovery circuit for burst-mode transmission” in Symposium on VLSI Circuits, Dig. Tech. Papers, pp. 122-123, June 1996.
[32] M. Nogawa, K. Nishimura, S. Kimura, T. Yoshida, T. Kawamura, M. Togashi, K. Kumozaki, and Y. Ohtomo, “A 10Gb/s burst-mode CDR IC in 0.13um CMOS,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, pp. 228-229, Feb. 2005.
[33] C. F. Liang, S. C. Hwu, S. I. Liu, “A 10Gbps burst-mode CDR circuit in 0.18um CMOS” IEEE Custom Integrated Circuits Conference(CICC), pp. 599-602, Sept. 2006
[34] J. Lee, “A 20-Gb/s adaptive equalizer in 0.13-um CMOS technology” IEEE J. Solid-State Circuits, vol. 41, pp. 2058-2066, Sept. 2006
[35] L. C. Cho, C. Lee, S. I. Liu, “A 33.6-to-33.8Gb/s burst-mode CDR in 90nm CMOS” IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, pp.48-49, Feb. 2007
[36] R. Adler, ” A study of locking phenomena in oscillators,” Proc. IEEE, vol. 61, pp. 1380-1385, Oct. 1973
[37] J. Lee and B. Razavi, “A 40-GHz frequency divider in 0.18um CMOS technology” IEEE J. Solid-State Circuits, vol. 39, pp. 594-601, April 2004
[38] T. Shibasaki, H. Tamura, K. Kanda, H. Yamaguchi, J. Ogawa, and T. Kuroda, “20-GHz quadrature Injection-Locked LC dividers with enhanced locking range,” IEEE J. Solid-State Circuits, vol. 43, pp. 610-618,March 2008.
[39] C. Lee and S. I. Liu, “A 35Gb/s limiting amplifier in 0.13um CMOS technology,” in Symposium on VLSI Circuits Dig. Tech. Papers, pp. 152-153, June 2006.
[40] S. Galal and B. Razavi, “40Gb/s amplifier and ESD protection circuit in 0.18um CMOS technology,” IEEE J. Solid-State Circuits, vol. 39, pp. 2389-2396, Dec. 2004
[41] J. Lee and M. Liu, “A 20Gb/s burst-mode CDR circuit using injection-locking technique” IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, pp.46-47, Feb. 2007
[42] B. Razavi, Design of Integrated Circuits for Optical Communications, New York: McGraw Hill, 2003.
[43] B. Razavi, “A study of Injection Locking and Pulling in Oscillators,” IEEE J. Solid-State Circuits, vol. 39, pp. 1415-1424 Sept. 2004.
[44] P. Mayr, C. Weyers, and U. Langmann, “A 90GHz 65nm CMOS injection-locked frequency divider” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Paper, pp.198-199, Feb. 2007
[45] D. Lim, J. Kim, J. Plouchart, C. Cho, D. Kim, R. Trzcinski, and D. Boning, “Performance variability of a 90GHz static CML frequency divider in 65nm SOI CMOS,”in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Paper, pp. 542-543, Feb. 2007.
[46] K.-H. Tsai, L.-C. Cho, J.-H. Wu and S.-I. Liu, “3.5mW W-band frequency divider with wide locking range in 90nm CMOS Technology”, International Solid-State Circuits Conference (ISSCC) 2008, pp. 466-467, Feb. 2008.
[47] S. Galal and B. Razavi, “40Gb/s amplifier and ESD protection circuit in 0.18um CMOS technology,” IEEE J. Solid-State Circuits, vol. 39, pp. 2389-2396, Dec. 2004
[48] C.-Y. Wu and C.-Y. Yu, “Design and analysis of a millimeter-wave direct injection-locked frequency divider with large frequency locking range” IEEE Trans. Microw. Theory Techn., vol.55, pp. 1649-1658, Aug. 2007
[49] F. Tzeng, D. Pi, A. Safarian, and P. Heydari, “Theoretical analysis of novel multi-order LC oscillators” IEEE Trans. On Circuit and System-II: Express briefs, vol.54, pp. 287-291, March 2007
dc.identifier.urihttp://tdr.lib.ntu.edu.tw/jspui/handle/123456789/26623-
dc.description.abstract隨著科技的發展與進步,需要越來越大的資料傳輸量,高速長距離通訊系統,幾乎都採用光纖通訊技術來達到廣泛的應用,其中,發射器中的時脈產生器與接收器中的時脈資料回復電路,皆在光纖通訊系統扮演關鍵性角色。
在此篇論文,首先,介紹一應用於光纖通訊的38GHz 0.13um CMOS時脈產生器,它採用八相位電感電容壓控振盪器(8-phase LC VCO),可以產生八個相位,高達38GHz輸出頻率的時脈訊號,論文中將會推導出,使用電容電感串接高通式架構,可以維持較高的頻率,並採用分布負載式除頻器(split-load frequency divider),可以有效的增加除頻器的操作頻率,最後採用能降低相位誤差的相位偵測器(phase detector),可以改善輸出的邊頻(frequency spur)。
第二,說明一應用於被動光纖網路(PON)通訊的34Gb/s 90nm CMOS 突發式時脈資料回復電路(burst mode CDR)。為了符合被動光纖網路多工控制的應用,它需要非常短的鎖定時間,為了減少依賴輸入資料產生的抖動(data dependent jitter),並且產生高速的時脈,採用了電感電容閘式壓控振盪器(LC Gated VCO),為了要接收寬頻的資料,採用一個寬頻輸入匹配電路以及一個寬頻資料緩衝器,最後採用相位選擇器,來預防因全速率(full-rate)操作下,可能產生的錯誤鎖定。
最後,除了完成以上光纖通訊關鍵電路,我們也提出一些可應用於未來的高速除頻器,高速除頻器一般採用注入鎖定式除頻器,因為可以產生最高的操作頻率以及較低的能量消耗。三種注入鎖定式除頻器,分別可以操作在72-78 GHz, 82.7-85.8GHz以及93.5~109.4GHz的範圍,論文中將會推導出,不同的架構,將會影響最高可操作的頻率以及可除頻範圍。
zh_TW
dc.description.abstractWith the development and advancement of technology, the more and more data transmission quantity is needed. High-speed and long-distance communication systems mostly adopt the optical networks in various applications. The clock generator for transmitter and the clock data recovery (CDR) for receiver play the critical roles.
First, a 38GHz clock generator in 0.13um CMOS is presented for optical communications. An 8-phase LC voltage-controlled oscillator is presented to generate the 8-phase 38GHz outputs. The highpass characteristic CL ladder topology sustains the high-frequency signals will be derived in this dissertation. The split-load divider is presented to extend the operation frequency. The phase detector (PD) improves the static phase error and improves the frequency spur.
Second, a 34Gb/s burse-mode CDR in 90nm CMOS is presented for passive optical network (PON) communications. The PON is attracting in the point-to-multipoint communication systems. It needs very short settling time. To reduce the data jitter and generate the high-frequency output clock, the LC gated voltage-controlled oscillator is presented. To receive and transmit the broadband data, a wideband input matching circuit and a wideband data buffer are presented, respectively. The phase selector is proposed to overcome the false phase lock due to the full-rate operation.
Finally, in addition to realize the above key components of optical communications, some high speed frequency divider is presented for future applications. The injection-locked frequency divider (ILFD) is attractive because the highest operation frequency and low power consumption. Three ILFDs have the locking range of 72-78 GHz, 82.7-85.8GHz and 93.5~109.4GHz, respectively. It will derive the center frequency and the locking range for different ILFDs.
en
dc.description.provenanceMade available in DSpace on 2021-06-08T07:17:57Z (GMT). No. of bitstreams: 1
ntu-97-D92943009-1.pdf: 7134894 bytes, checksum: 1b4629717722b37774b672215336cf08 (MD5)
Previous issue date: 2008
en
dc.description.tableofcontents1. Introduction………………………………………………………… 1
1.1 Optical Communication...…………………..……………….. 1
1.2 RF front-end overview……...……….…………….……….... 4
1.3 Specifications……………….……….…………….……….... 6
1.4 Organization…………………………………………………. 8

2. The Basics of PLL and CDR……………………………...………... 9
2.1 Phase-Locked Loop………………………………………….. 10
2.2 PLL noise analysis…………………..……………………….. 18
2.3 Clock and Data Recovery Circuit..…….…………………….. 22
2.4 Jitter analysis of CDR………..…………………………….... 26
2.5 Conclusion………………………………………………….... 30
3. A 37-38.5GHz 8-phase Clock Generator………………...………... 31
3.1 Introduction…………………………………………………... 32
3.2 Circuit Description…………………..……………………….. 33
3.3 Experimental Results…..…….….……..…………………….. 54
3.4 Conclusion………………………………………………….... 67
4. A 33.6-33.8Gb/s Burst-Mode CDR…………………………….….. 69
4.1 Introduction………………………..……………….………... 70
4.2 Circuit Description……………….………………………….. 75
4.3 Experimental Results…..……….………….………………… 94
4.4 Conclusion….……………………………………………….. 100
5. Categories of Frequency Dividers………………………………… 103
5.1 FlipFlop-Based Frequency Dividers…..…….......................... 104
5.2 Miller Dividers…..…….…………………………..……….... 105
5.3 Injection-locked Frequency Dividers………….….……….… 108
5.4 Conclusion……………………………………….……….….. 110
6. W-band Injection-locked Frequency Dividers………………..…... 111
6.1 Introduction………………………..……………….………... 112
6.2 Circuit Description……………….………………………….. 113
6.3 Simulated Results…..……….………….………………… 122
6.4 Experimental Results…..……….………….………………… 124
6.5 Conclusion……………………………………………….…... 132
7. Conclusion…………………………………………………………... 135
7.1 Conclusion………………………………………………….... 135
7.2 Future Work…………….…………………………..………... 137
Bibliography………………………………………………………... 139
Publication List……………………………………………………... 143
dc.language.isoen
dc.title應用於光通訊之時脈產生器與突發式時脈資料回復電路zh_TW
dc.titleClock Generator and Burst-Mode CDR for Optical Communicationsen
dc.typeThesis
dc.date.schoolyear96-2
dc.description.degree博士
dc.contributor.oralexamcommittee薛福隆(Fu-Long Xue),林宗賢(Tsung-Hsien Lin),郭泰豪(Tai-Haur Kuo),楊清淵(Ching-Yuan Yang),鄭國興(Kuo-Hsing Cheng),周世傑(Shyh-Jye Jou),李泰成(Tai-Cheng Lee)
dc.subject.keyword鎖相迴路:多相位:資料回復電路:除法器,zh_TW
dc.subject.keywordPLL:Multi-phase:CDR:divider,en
dc.relation.page141
dc.rights.note未授權
dc.date.accepted2008-07-28
dc.contributor.author-college電機資訊學院zh_TW
dc.contributor.author-dept電子工程學研究所zh_TW
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