高速類比適應式等化器之設計及實作

Abstract

在逐漸提升頻率的訊號傳輸領域中及有限的通道頻寬(Channel Bandwidth)下，如何增加資料的傳輸並減少其錯誤率為越來越重要的課題。等化器一直是高頻傳輸系統架構中的重要電路。尤其當傳輸速率到達數億赫茲，使用類比電路實現的等化器，且為了適應通道隨溫度及時間的變化，採用適應式的電路架構，對於訊號的回復更是一個可行的方式。本論文探討使用濾波器方式實現的可調控式類比等化器電路，利用變容器及操作在三極體區的電晶體當電阻作為調控機制。此等化器使用TSMC 0.18μm 1P6M CMOS製程。

Nowadays, data transmission operates at a very high speed. However as the transmission data rate becomes higher, the signal suffers from more severe frequency dependent magnitude loss due to the channel limited bandwidth. Analog adaptive equalizer has been proven of great use to compensate the non-ideality. Along with the adaptability, analog equalizer is capable of giving adequate boosting to time and temperature varying channel loss. In the Thesis, an analog filter fabricated in TSMC 0.18μm 1P6M CMOS technology is designed. MOS varactor and transistor in triode region acts as variable resistor is applied for adaptability.