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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/25060完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 陳少傑(Sao-Jei Chen) | |
| dc.contributor.author | Jui-Chieh Lin | en |
| dc.contributor.author | 林叡杰 | zh_TW |
| dc.date.accessioned | 2021-06-08T06:01:19Z | - |
| dc.date.copyright | 2007-07-30 | |
| dc.date.issued | 2007 | |
| dc.date.submitted | 2007-07-27 | |
| dc.identifier.citation | [1] B. Razavi, Design of Integrated Circuits for Optical Communications, McGraw-Hill, Inc., 2003.
[2] J. S. Choi, M. S. Hwang, and D.K. Jeong, “A 0.18-μm CMOS 3.5-Gb/s Continuous-Time Adaptive Cable Equalizer Using Enhanced Low-Frequency Gain Control Method,” IEEE Journal of Solid-State Circuits, vol. 39, no. 3, pp. 419–425, Mar. 2004. [3] G. E. Zhang and M. M. Green, “A 10 Gb/s BiCMOS Adaptive Cable Equalizer,” IEEE Journal of Solid-State Circuits, vol. 40, no. 11, pp. 2132–2139, Nov. 2005. [4] S. Gondi, J. Lee, D. Takeuchi, and B. Razavi, “A 10Gb/s CMOS Adaptive Equalizer for Backplane Applications,” in Proc. IEEE International Solid State Circuit Conference, pp. 328-329, Feb. 2005. [5] J. N. Babanezhad, “A 3.3-V Analog Adaptive Line-Equalizer for Fast Ethernet Data Connection,” in Proc. IEEE Custom Integrated Circuit Conference, pp. 343–346, May 1998. [6] D. W. Chou,”A-10Gb/s Adaptive Equalizer in 0.18-μm CMOS Technology,” Master Thesis, National Taiwan University, Taipei, Taiwan, Jul. 2005. [7] Y. Tomita, M. Kibune, J. Ogawa, W. W. Walker, H. Tamura, and T. Kuroda, “A l0Gb/s Receiver with Equalizer and On-chip IS1 Monitor in 0.11μm CMOS,” in Proc. IEEE Symposium On VLSl Circuits Digest of Technical Papers, pp. 205-205, Jun. 2004. [8] M. M. Green and U. Singh, “Design of CMOS CML Circuits for High-Speed Broadband Communications,” in Proc. IEEE Int. Symp. Circuits and Systems, vol. II, pp. 204-207, May 2003. [9] C. D. Holdenried, M. W. Lynch, and J. W. Haslett, “Modified CMOS Cherry-Hooper Amplifiers with Source Follower Feedback in 0.35 μm Technology,” in IEEE Proceedings of the 29th European Solid-State Circuits Conference (ESSCIRC), pp. 553-556, Sep. 2003. [10] E. M. Cherry and D. E. Hooper, “The Design of Wideband Transistor Feedback Amplifier,” Institution of Electronic Engineering Roc., vol.110, no. 2, pp. 375-389, Feb. 1963. [11] R. L. Bunch and S. Raman,” Large-Signal Analysis of MOS Varactors in CMOS Gm-LC VCOs,” IEEE Journal of Solid-State Circuits, vol. 38, no. 8, pp. 1325–1332, Aug. 2003. [12] Y. Kudoh, M. Fukaishi, and M. Mizuno, “A 0.13-μm CMOS 5-Gb/s 10-m 28AWG Cable Transceiver with No-feedback-loop Continuous-time Post-equalizer,” IEEE Journal of Solid-State Circuits, vol. 38, no. 5, pp. 741–746, Mar. 2004. [13] J. Lee, “High-Speed Circuit Designs for Transmitters in Broadband Data Links,” IEEE Solid State Circuit Conference, Digital Object Identifier, pp. 1004-1015, May 2006. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/25060 | - |
| dc.description.abstract | 在逐漸提升頻率的訊號傳輸領域中及有限的通道頻寬(Channel Bandwidth)下，如何增加資料的傳輸並減少其錯誤率為越來越重要的課題。等化器一直是高頻傳輸系統架構中的重要電路。尤其當傳輸速率到達數億赫茲，使用類比電路實現的等化器，且為了適應通道隨溫度及時間的變化，採用適應式的電路架構，對於訊號的回復更是一個可行的方式。本論文探討使用濾波器方式實現的可調控式類比等化器電路，利用變容器及操作在三極體區的電晶體當電阻作為調控機制。此等化器使用TSMC 0.18μm 1P6M CMOS製程。 | zh_TW |
| dc.description.abstract | Nowadays, data transmission operates at a very high speed. However as the transmission data rate becomes higher, the signal suffers from more severe frequency dependent magnitude loss due to the channel limited bandwidth. Analog adaptive equalizer has been proven of great use to compensate the non-ideality. Along with the adaptability, analog equalizer is capable of giving adequate boosting to time and temperature varying channel loss. In the Thesis, an analog filter fabricated in TSMC 0.18μm 1P6M CMOS technology is designed. MOS varactor and transistor in triode region acts as variable resistor is applied for adaptability. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-08T06:01:19Z (GMT). No. of bitstreams: 1 ntu-96-R94943108-1.pdf: 1345844 bytes, checksum: 49f2a97f112fcd6e5564879b7623e945 (MD5) Previous issue date: 2007 | en |
| dc.description.tableofcontents | 第一章 簡介 伍
第二章 等化器簡介 陸 第三章 類比等化器設計 柒 第四章 類比等化器之實作 捌 第五章 結論 玖 -------------------------------------- ABSTRACT i LIST OF FIGURES v LIST OF TABLES vii CHAPTER 1 INTRODUCTION 1 1.1 Motivation……………..………………………………………………….1 1.2 Thesis Organization……………………………………………………..1 CHAPTER 2 BASIC CONCEPT of EQUALIZER..….…………………………...3 2.1 Random Binary Sequence……………………………………………….3 2.2 Eye Diagram……………………………………………………………..5 2.3 Bit Error Rate..……………………………………………………………7 2.4 Analysis of Transmission Line…………………………………………9 CHAPTER 3 DESIGN OF ANALOG ADAPTIVE EQUALIZER……….…….13 3.1 System Overview...……………………………………………..……....13 3.2 Equalizing Filter…………………………………………………………19 3.3 Gain Stage……….………………………………………………………23 3.4 Slicer…………...………………………………………………………25 3.5 Rectifier…………………………………………………………………27 3.6 Charge Pump……………………………………………………………29 3.7 High-Pass and Low-Pass Filter....………………………………………30 CHAPTER 4 IMPLEMENTATION OF ANALOG ADAPTIVE EQUALIZER.31 4.1 Equalizer Closed Loop Transistor Level Simulation Results……………31 4.2 Comparison with Conventional Architecture……………………………36 4.3 Chip Layout of the Proposed Equalizer…….…………………………39 4.4 Performance Summary……….……………………..…………………40 CHAPTER 5 CONCLUSION……………..............................................................41 REFERENCE…….......................................................................................................43 | |
| dc.language.iso | en | |
| dc.title | 高速類比適應式等化器之設計及實作 | zh_TW |
| dc.title | Design and Implementation of a High-Speed Analog Adaptive Equalizer | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 95-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.coadvisor | 張棋(Chi Chang) | |
| dc.contributor.oralexamcommittee | 李泰成(Tai-Cheng Lee),林宗賢(Tsung-Hsien Lin),游竹(Chu Yu) | |
| dc.subject.keyword | 等化器,類比等化器,連續時間濾波器,接收器, | zh_TW |
| dc.subject.keyword | equalizers,adaptive equalizers,continuous time filters,receiver, | en |
| dc.relation.page | 44 | |
| dc.rights.note | 未授權 | |
| dc.date.accepted | 2007-07-30 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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|---|---|---|---|
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