多重編碼率低密度奇偶校正碼之解碼器 適用於IEEE 802.16e

Abstract

Because of its excellent bit-error-rate performance, the Low-Density Parity- Check (LDPC) Code was adopted in standards of IEEE 802.16e (Metropoli- tan Area Network). The IEEE 802.16e LDPC code currently consists of six di®erent code classes spanning four di®erent code rates (1/2, 2/3, 3/4 and 5/6) and support variable code length. In this thesis, we present a multi- rate LDPC decoder architecture for IEEE 802.16e. Our overlapping schedule can improve the latency of the block-serial layered decoder architecture by 1.7x-2.7x, with a small hardware requirements. The proposed architecture adopts layer decoding algorithm with scaling min-sum approximation and utilizes value-reuse property of min-sum approximation to save memory re- quirement of LDPC decoder. The decoding throughput of the decoder can achieve 500Mbps.