請用此 Handle URI 來引用此文件：
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/25000完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 顧孟愷(Mong-kai ku) | |
| dc.contributor.author | Yu-Min Chang | en |
| dc.contributor.author | 張育民 | zh_TW |
| dc.date.accessioned | 2021-06-08T05:59:57Z | - |
| dc.date.copyright | 2007-08-28 | |
| dc.date.issued | 2007 | |
| dc.date.submitted | 2007-07-30 | |
| dc.identifier.citation | Bibliography
[1] R. Gallager, Low-density parity-check codes,' Information Theory, IEEE Transactions on, vol. 8, no. 1, pp. 21{28, 1962. [2] R. Tanner, A recursive approach to low complexity codes,' Information Theory, IEEE Transactions on, vol. 27, no. 5, pp. 533{547, 1981. [3] D. MacKay and R. Neal, Near Shannon limit performance of low den- sity parity check codes,' Electronics Letters, vol. 33, no. 6, pp. 457{458, 1997. [4] T. Richardson and R. Urbanke, The capacity of low-density parity- check codes under message-passing decoding,' IEEE Transactions on Information Theory, vol. 47, no. 2, pp. 599{618, 2001. [5] Digital Video Broadcasting (DVB) Second generation framing structure for broadband satellite applications, ETSI Std. EN 302 307 v1.1.1, 2005. [6] High Throughput extension to the 802.11 Standard, IEEEWorking Draft Proposed Standard 802.11n, 2007. [7] D. Cho, J. Song, M. Kim, and K. Han, Performance Analysis of the IEEE 802.16 Wireless Metropolitan Area Network,' International 59 Conference on Distributed Frameworks for Multimedia Applications, pp. 130{136, 2005. [8] Y. Kou, S. Lin, and M. Fossorier, Low-density parity-check codes based on ‾nite geometries: arediscovery and new results,' Information Theory, IEEE Transactions on, vol. 47, no. 7, pp. 2711{2736, 2001. [9] M. Khojastepour, N. Ahmed, and B. Aazhang, Code design for the re- lay channel and factor graph decoding,' Signals, Systems and Comput- ers, 2004. Conference Record of the Thirty-Eighth Asilomar Conference on, vol. 2, 2004. [10] T. Richardson, M. Shokrollahi, and R. Urbanke, Design of capacity- approaching irregular low-density parity-checkcodes,' Information The- ory, IEEE Transactions on, vol. 47, no. 2, pp. 619{637, 2001. [11] R. Tanner, D. Sridhara, and T. Fuja, A class of group-structured LDPC codes,' Proc. of ICSTA, 2001. [12] J. Chen, R. Tanner, J. Zhang, and M. Fossorier, Construction of Ir- regular LDPC Codes by Quasi-Cyclic Extension,' Information Theory, IEEE Transactions on, vol. 53, no. 4, pp. 1479{1483, 2007. [13] Local and metropolitan area networks Part 16: Air Interface for Fixed and Mobile Broadband Wirelesss Access Systems Amendment 2: Physi- cal and Medium Access Control Layers for Combined Fixed and Mobile Operation in Licensed Bands and Corrigendum 1, IEEE Std. 802.16e, 2006. 60 [14] S. Lin and D. Costello, Error Control Coding: Fundamentals and Ap- plications. Prentice-Hall, 1983. [15] F. Kschischang, B. Frey, and H. Loeliger, Factor graphs and the sum- product algorithm,' IEEE Transactions on Information Theory, vol. 47, no. 2, pp. 498{519, 2001. [16] M. Fossorier, M. Mihaljevic, and H. Imai, Reduced complexity iterative decoding of low-density parity check codes based on belief propagation,' Communications, IEEE Transactions on, vol. 47, no. 5, pp. 673{680, 1999. [17] H. Song and P. Zhang, Optimum o®set factor of LDPC codes,' Elec- tronics Letters, vol. 39, no. 14, pp. 1065{1066, 2003. [18] J. Heo, Analysis of scaling soft information on low density parity check code,' Electronics Letters, vol. 39, no. 2, pp. 219{221, 2003. [19] J. Dielissen, A. Hekstra, and V. Berg, Low cost LDPC decoder for DVB-S2,' Proceedings of the conference on Design, automation and test in Europe: Designers' forum, pp. 130{135, 2006. [20] J. Heo and K. Chugg, Optimization of scaling soft information in iter- ative decoding via density evolution methods,' Communications, IEEE Transactions on, vol. 53, no. 6, pp. 957{961, 2005. [21] D. Oh and K. Parhi, Performance of Quantized Min-Sum Decoding Algorithms for Irregular LDPC Codes,' Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on, pp. 2758{2761, 2007 | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/25000 | - |
| dc.description.abstract | Because of its excellent bit-error-rate performance, the Low-Density Parity-
Check (LDPC) Code was adopted in standards of IEEE 802.16e (Metropoli- tan Area Network). The IEEE 802.16e LDPC code currently consists of six di®erent code classes spanning four di®erent code rates (1/2, 2/3, 3/4 and 5/6) and support variable code length. In this thesis, we present a multi- rate LDPC decoder architecture for IEEE 802.16e. Our overlapping schedule can improve the latency of the block-serial layered decoder architecture by 1.7x-2.7x, with a small hardware requirements. The proposed architecture adopts layer decoding algorithm with scaling min-sum approximation and utilizes value-reuse property of min-sum approximation to save memory re- quirement of LDPC decoder. The decoding throughput of the decoder can achieve 500Mbps. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-08T05:59:57Z (GMT). No. of bitstreams: 1 ntu-96-R94922154-1.pdf: 2775826 bytes, checksum: 897c30b15b2bd6347557f27e21e84376 (MD5) Previous issue date: 2007 | en |
| dc.description.tableofcontents | Contents
1 Introduction 1 1.1 Low-Density Parity-Check Codes . . . . . . . . . . . . . . . . 2 1.2 Irregualr LDPC Codes . . . . . . . . . . . . . . . . . . . . . . 4 1.3 Structure LDPC Codes . . . . . . . . . . . . . . . . . . . . . . 5 1.3.1 Quasi-cyclic LDPC Codes . . . . . . . . . . . . . . . . 7 1.3.2 LDPC Codes for WiMAX . . . . . . . . . . . . . . . . 8 1.4 Thesis Organization . . . . . . . . . . . . . . . . . . . . . . . . 13 2 LDPC Decoding Algorithm 14 2.1 LDPC Decoding Algorithm . . . . . . . . . . . . . . . . . . . 14 2.1.1 Sum-Product Algorithm . . . . . . . . . . . . . . . . . 15 2.1.2 Layer Decoding Algorithm . . . . . . . . . . . . . . . . 19 2.2 Min-Sum Apprxoimation . . . . . . . . . . . . . . . . . . . . . 21 2.2.1 Min-Sum . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.2.2 O®set Min-Sum . . . . . . . . . . . . . . . . . . . . . . 21 2.2.3 Scaling Min-Sum . . . . . . . . . . . . . . . . . . . . . 22 2.2.4 Value-Reuse Property . . . . . . . . . . . . . . . . . . 22 2.3 Software Simulation Results . . . . . . . . . . . . . . . . . . . 23 ii 2.3.1 Double Precision . . . . . . . . . . . . . . . . . . . . . 23 2.3.2 Finite Word Length . . . . . . . . . . . . . . . . . . . . 27 3 Multi-Rate LDPC Decoder Architecture 29 3.1 An Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.2 Memory Block . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.2.1 Channel Information Memory Banks . . . . . . . . . . 31 3.2.2 Check Information Magnitude Memory Banks . . . . . 31 3.2.3 Check Information Sign Bit Memory Bank . . . . . . . 32 3.2.4 Bit Information Memory Bank . . . . . . . . . . . . . . 33 3.2.5 Permutation Rom Bank . . . . . . . . . . . . . . . . . 33 3.2.6 Channel Information Access Order Rom Bank . . . . . 33 3.3 Process Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.3.1 Rotator . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.3.2 Get Bit Information Unit Bank . . . . . . . . . . . . . 35 3.3.3 Serial Processing Unit Bank . . . . . . . . . . . . . . . 36 3.3.4 Get Channel Information Unit Bank . . . . . . . . . . 36 3.3.5 Control Unit . . . . . . . . . . . . . . . . . . . . . . . . 38 3.4 Schedule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.4.1 Original Schedule . . . . . . . . . . . . . . . . . . . . . 39 3.4.2 After Rearrange Memory Access Order . . . . . . . . . 40 4 Implementation Results 47 4.1 Hardware Development Environments . . . . . . . . . . . . . . 47 4.1.1 FPGA Board . . . . . . . . . . . . . . . . . . . . . . . 47 4.1.2 Altra Quarts II . . . . . . . . . . . . . . . . . . . . . . 48 iii 4.1.3 Altera NIOS II . . . . . . . . . . . . . . . . . . . . . . 48 4.2 Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 4.3 Veri‾ed Platform . . . . . . . . . . . . . . . . . . . . . . . . . 51 4.4 Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 5 Conclusion and Future Work 57 5.1 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 5.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 | |
| dc.language.iso | en | |
| dc.subject | 低密度奇偶校正碼 | zh_TW |
| dc.subject | IEEE 802.16e | en |
| dc.subject | LDPC | en |
| dc.title | 多重編碼率低密度奇偶校正碼之解碼器
適用於IEEE 802.16e | zh_TW |
| dc.title | Multi-Rate LDPC Decoder for IEEE 802.16e | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 95-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 陳信樹,林宗男,廖俊睿 | |
| dc.subject.keyword | 低密度奇偶校正碼, | zh_TW |
| dc.subject.keyword | LDPC,IEEE 802.16e, | en |
| dc.relation.page | 61 | |
| dc.rights.note | 未授權 | |
| dc.date.accepted | 2007-07-31 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 資訊工程學研究所 | zh_TW |
| 顯示於系所單位： | 資訊工程學系 | |
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|---|---|---|---|
| ntu-96-1.pdf 未授權公開取用 | 2.71 MB | Adobe PDF |
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