改善週期式滑脫現象之一個1.5-6 Gb/s時脈與資料回復電路

Abstract

提出的CDR電路以40nm CMOS製程模擬，在1V電源供應下，可操作在1.5Gb/s到6Gb/s。在輸入資料率為6Gb/s時，功率消耗大約為4.43mW。根據模擬結果可證明此論文提出的CDR電路具有雙向追頻率的功能，可以避免在頻率鎖定後，輸入的資料率突然改變，或因雜訊的擾動導致VCO頻率發生變化，CDR電路卻不能重新與輸入頻率鎖定的問題。同時改善了傳統雙迴路CDR電路中會面臨的週期式滑脫現象，並加快頻率獲取的速度。

The proposed CDR circuit is simulated in 40-nm CMOS technology. While the supply is 1-V, the CDR circuit can operate with the data rate of 1.5-6 Gb/s. The power consumption is about 4.43mW when the input data rate is 6Gb/s. According to the simulation results, it can prove that the proposed CDR circuit is able to track the frequency bi-directionally, and acquire the data rate again if the data rate changes or a noise on control voltage make the clock frequency change. Also, it is reduced with the cycle slipping issue which happens a lot in traditional dual-loop CDRs. And the frequency acquisition time is improved, too.