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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 劉深淵(Shen-Iuan Liu) | |
| dc.contributor.author | Wei-Liang Lin | en |
| dc.contributor.author | 林偉良 | zh_TW |
| dc.date.accessioned | 2021-06-08T03:32:13Z | - |
| dc.date.copyright | 2019-08-19 | |
| dc.date.issued | 2019 | |
| dc.date.submitted | 2019-08-11 | |
| dc.identifier.citation | [1] R. J. Yang, K. H. Chao, S. C. Hwu, C. K. Liang, and S. I. Liu, “A 155.52 Mbps ~ 3.125 Gbps continuous-rate clock and data recovery,” IEEE J. Solid-State Circuits, vol. 41, no. 6, pp. 1380–1390, Jun. 2006.
[2] S. Choi, H. Son, J. Shin, S. H. Lee, B. Kim, H. J. Park, and J. Y. Sim, “A 0.65-to-10.5 Gb/s reference-less CDR with asynchronous baud-rate sampling for frequency acquisition and adaptive equalization,” IEEE Trans. Circuits Syst. I, Regular Papers, vol. 63, no. 2, pp. 276–287, Feb. 2016. [3] R. Inti, W. Yin, A. Elshazly, N. Sasidhar, and P. K. Hanumolu, “A 0.5-to-2.5 Gb/s reference-less half-rate digital CDR with unlimited frequency acquisition range and improved input duty-cycle error tolerance,” IEEE Int. Solid-State Circuits Conf., Feb. 2011, pp. 438–440. [4] G. Shu, W. S. Choi, S. Saxena, T. Anand, A. Elshazly, and P. K. Hanumolu, “A 4-to-10.5Gb/s 2.2mW/G/s continuous-rate digital CDR with automatic frequency acquisition in 65nm CMOS,” IEEE Int. Solid-State Circuits Conf., Feb. 2014, pp. 150–152. [5] M. T. Hsieh and G. E. Sobelman, “Architectures for multi-gigabit wire-linked clock and data recovery,” IEEE Circuits and Systems Magazine, vol. 8, pp. 45-57, Fourth Quarter 2008. [6] R. Shivnaraine, M. S. Jalali, A. Sheikholeslami, M. Kibune, and H. Tamura, “An 8–11 Gb/s reference-less bang-bang CDR enabled by “phase reset”,” IEEE Trans. Circuits Syst. I, Regular Papers, vol. 61, no. 7, pp. 2129-2138, Feb. 2014. [7] M. S. Jalali, A. Sheikholeslami, M. Kibune, and H. Tamura, “A reference-less single-loop half-rate binary CDR,” IEEE J. Solid-State Circuits, vol. 50, no. 9, pp. 2037–2047, Sept. 2015. [8] S. Huang, J. Cao, and M. M. Green, “An 8.2 Gb/s-to-10.3 Gb/s full-rate linear referenceless CDR without frequency detector in 0.18 μm CMOS,” IEEE J. Solid-State Circuits, vol. 50, no. 9, pp. 2048–2060, Sept. 2015. [9] S. Byun, “A 400 Mb/s∼2.5 Gb/s referenceless CDR IC using intrinsic frequency detection capability of half-rate linear phase detector,” IEEE Trans. Circuits Syst. I, Regular Papers, vol. 63, no. 10, pp. 1592–1604, Oct. 2016. [10] H. H. Chang, S. I. Liu, “A wide-range and fast-locking all-digital cycle-controlled delay-locked loop,” IEEE J. Solid-State Circuits, vol. 40, no. 3, pp. 661-670, Mar. 2005. [11] S. K. Lee, Y. S. Kim, H. Ha, Y. Seo, H. J. Park, and J. Y. Sim, “A 650Mb/s-to-8Gb/s referenceless CDR circuit with automatic acquisition of data rate,” IEEE Int. Solid-State Circuits Conf., pp. 184-186, Feb. 2009. [12] K. Yamaguchi, Y. Hori, K. Nakajima, K. Suzuki, M. Mizuno, and H. Hayama, “A 2.0 Gb/s clock-embedded interface for full-HD 10-bit 120 Hz LCD drivers with 1/5-rate noise-tolerant phase and frequency recovery,” IEEE J. Solid-State Circuits, vol. 44, no. 12, pp. 3560-3567, Dec. 2009. [13] H. H. Chang, J. Y. Chang, C. Y. Kuo, S. I. Liu, “A 0.7-2-GHz self-calibrated multiphase delay-locked loop,” IEEE J. Solid-State Circuits, vol. 41, no. 5, pp. 1051-1061, May. 2006. [14] L. Sun, and T. A. Kwasniewski, “A 1.25-GHz 0.35-um monolithic CMOS PLL based on a multiphase ring oscillator,” IEEE J. Solid-State Circuits, vol. 36, no. 6, pp. 910-916, Jun. 2001. [15] C. L. Hsieh and S. I. Liu, “A 1-16-Gb/s wide-range clock/data recovery circuit with a bidirectional frequency detector,” IEEE Trans. Circuits Syst. II: Express Briefs, vol. 58, no. 8, pp. 487-491, Aug. 2011. [16] R. J. Yang, K. H. Chao, and S. I. Liu, “A 200 Mbps ~ 2 Gbps continuous-rate clock and data recovery,” IEEE Trans. Circuits Syst. I: Regular Paper, vol. 53, no. 4, pp. 842-847, Apr. 2006. [17] B. Razavi, Design of Integrated Circuits for Optical Communications. John Wiley & Sons. Inc., 2012. [18] J. Lee, K. Kundert, and B. Razavi, “Analysis and modeling of bang-bang clock and data recovery circuits,” IEEE Journal of Solid-State Circuits, vol. 39, pp. 1571-1580, Sept. 2004. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/21368 | - |
| dc.description.abstract | 提出的CDR電路以40nm CMOS製程模擬，在1V電源供應下，可操作在1.5Gb/s到6Gb/s。在輸入資料率為6Gb/s時，功率消耗大約為4.43mW。根據模擬結果可證明此論文提出的CDR電路具有雙向追頻率的功能，可以避免在頻率鎖定後，輸入的資料率突然改變，或因雜訊的擾動導致VCO頻率發生變化，CDR電路卻不能重新與輸入頻率鎖定的問題。同時改善了傳統雙迴路CDR電路中會面臨的週期式滑脫現象，並加快頻率獲取的速度。 | zh_TW |
| dc.description.abstract | The proposed CDR circuit is simulated in 40-nm CMOS technology. While the supply is 1-V, the CDR circuit can operate with the data rate of 1.5-6 Gb/s. The power consumption is about 4.43mW when the input data rate is 6Gb/s. According to the simulation results, it can prove that the proposed CDR circuit is able to track the frequency bi-directionally, and acquire the data rate again if the data rate changes or a noise on control voltage make the clock frequency change. Also, it is reduced with the cycle slipping issue which happens a lot in traditional dual-loop CDRs. And the frequency acquisition time is improved, too. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-08T03:32:13Z (GMT). No. of bitstreams: 1 ntu-108-R04943135-1.pdf: 1796196 bytes, checksum: fda3d69a8d30b162e609771e6eec6cad (MD5) Previous issue date: 2019 | en |
| dc.description.tableofcontents | 口試委員會審定書 i
摘要 ii Abstract iii 第一章、緒論 1 第二章、時脈資料回復電路種類與提出之架構 3 2.1 時脈資料回復電路種類 3 2.1.1 以鎖相迴路為基礎 3 2.1.2 以鎖相迴路/延遲鎖定迴路的結合為基礎 3 2.1.3 以相位內差器為基礎 4 2.1.4 以閘式振盪器為基礎 4 2.2 一個1.5-6 GB/S時脈與資料回復電路架構 6 2.2.1 fVCO 小於 fb 7 2.2.2 fVCO 大於 fb 7 2.2.3 改良型線性相位偵測器 8 2.2.4 改良型單向頻率偵測器 11 2.2.5 VCO的頻段選擇機制 12 2.3 頻率獲取範圍 13 2.3.1 計算迴路參數 13 2.3.2 模擬全速率線性相位偵測器的頻率獲取範圍 14 2.3.3 推導fVCO的方程式 14 2.3.4 決定ICF電流 15 第三章、電路實現 18 3.1 VCO電路 18 3.2 CHARGE PUMP (CP)電路 20 3.3 D型正反器電路 21 3.4 D型閂鎖器電路 22 3.5 改良型線性相位偵測器之設計考量 24 3.6 整體佈局 25 第四章、I/O 介面模型與模擬結果 26 4.1 I/O介面模型 26 4.1.1 輸入介面模型 26 4.1.2 輸出介面模型 27 4.2 模擬結果 29 4.2.1 fVCO 小於 fb 29 4.2.2 fVCO 大於 fb 30 第五章、結論 31 參考資料 32 | |
| dc.language.iso | zh-TW | |
| dc.title | 改善週期式滑脫現象之一個1.5-6 Gb/s時脈與資料回復電路 | zh_TW |
| dc.title | A 1.5-6 Gb/s Clock and Data Recovery Circuit Reducing Cycle Slipping | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 107-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 林宗賢(Tsung-Hsien Lin),李泰成(Tai-Cheng Lee) | |
| dc.subject.keyword | 時脈與資料回復,寬範圍,無參考時脈,週期式滑脫, | zh_TW |
| dc.subject.keyword | Clock and data recovery (CDR),wide-range,reference-less,cycle slipping, | en |
| dc.relation.page | 34 | |
| dc.identifier.doi | 10.6342/NTU201901065 | |
| dc.rights.note | 未授權 | |
| dc.date.accepted | 2019-08-12 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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