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Title: | 具選擇性誤差調變及雜訊調變之十三位元六千四百萬取樣頻率連續漸進式類比數位轉換器 A 13-bit 64MS/s Noise-Shaping Successive-Approximation A/D Converter with Selective Mismatch Error Shaping |
Authors: | Wei-Cian Hong 洪瑋謙 |
Advisor: | 李泰成(Tai-Cheng Lee) |
Keyword: | 類比數位轉換器,動態放大器,數位類比轉換器之誤差調變,雜訊調變,誤差回饋,超取樣類比數位轉換器,連續漸進式, Analog-to-digital converter (ADC),dynamic amplifier,DAC mismatch error shaping,noise shaping,error feedback (EF) structure,oversampling ADC,successive-approximation-register (SAR)., |
Publication Year : | 2020 |
Degree: | 碩士 |
Abstract: | 本論文提出一個具有具選擇性誤差調變及雜訊調變之十三位元六千四百萬取樣頻率連續漸進式類比數位轉換器,三階的雜訊調變由誤差回饋的架構來實現,其中量化誤差回饋的架構採用動態比較器來重複做為動態放大器以及被動有限脈衝響應來達成,而在非線性的部分,主要由電容式數位類比轉換器中的電容所造成,而選擇性誤差調變則改善了上述非線性的問題。本晶片使用台積電四十奈米互補式金屬氧化物半導體製程所實現,本晶片操作於六千四百萬取樣頻率,並於超取樣率為10.66下得到71 dB的訊號雜訊失真比,達到Schreier品質因素(FoM)為160 dB以及Walden品質因素為50fJ/conversion-step。在1.2伏特的電源供應下總共消耗869微瓦,晶片的核心面積小於0.03平方毫米。 This thesis presents a 3rd-order noise-shaping successive-approximation register (SAR) ADC with selective mismatch error shaping. A 3rd-order noise shaping is achieved by implementing an error-feedback (EF) structure with comparator-reused dynamic amplifier and passive finite impulse response (FIR). The non-linearity resulting from capacitor mismatch is minimized by employing selective mismatch error shaping (MES). Fabricated in 40-nm CMOS, the prototype chip achieves a peak SNDR of 71 dB when operating at 64MS/s with an over-sampling ratio (OSR) of 10.66. The Schreier FoM is 160 dB, and the Walden FoM is 50 fJ/conversion-step. This chip occupies an active area smaller than 0.03 mm2 and consumes 869 μW with a 1.2-V supply. |
URI: | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/21089 |
DOI: | 10.6342/NTU202000152 |
Fulltext Rights: | 未授權 |
Appears in Collections: | 電子工程學研究所 |
Files in This Item:
File | Size | Format | |
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ntu-109-1.pdf Restricted Access | 6.59 MB | Adobe PDF |
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