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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 李泰成(Tai-Cheng Lee) | |
dc.contributor.author | Wei-Cian Hong | en |
dc.contributor.author | 洪瑋謙 | zh_TW |
dc.date.accessioned | 2021-06-08T03:26:51Z | - |
dc.date.copyright | 2020-02-05 | |
dc.date.issued | 2020 | |
dc.date.submitted | 2020-01-16 | |
dc.identifier.citation | [1] B. Razavi, “Design Considerations for Interleaved ADCs,” IEEE J. Solid-State Circuits, vol. 48, no. 8, pp. 1806–1817, Aug. 2013.
[2] R. E. Suarez, P. R. Gray, D. A. Hodges, “An all-MOS Charge-Redistribution A/D Conversion Technique”, in ISSCC Dig. Tech. Papers, Feb. 1974, pp. 194 - 195. [3] S. Chen and R. Brodersen, “A 6-bit 600-MS/s 5.3-mW Asynchronous ADC in 0.13- μm CMOS,” IEEE J. Solid-State Circuits, vol. 41, no. 12, pp. 2669–2680, Dec. 2006. [4] J. A. Fredenburg and M. P. Flynn, “A 90-MS/s 11-MHz-Bandwidth 62-dB SNDR Noise-Shaping SAR ADC,” IEEE J. Solid-State Circuits, vol. 47, no. 12, pp. 2898–2904, Dec. 2012. [5] P. Payandehnia, H. Mirzaie, H. Maghami, J. Muhlestein and G.C. Temes, “Fully Passive Third-Order Noise Shaping SAR ADC,” in Electronics Letters, April 2017, vol. 53 no. 8 pp. 528–530. [6] S. Li, B. Qiao, M. Gandara, D. Z. Pan, and N. Sun, “A 13-ENOB Second-Order Noise-Shaping SAR ADC Realizing Optimized NTF Zeros Using the Error-Feedback Structure,” IEEE J. Solid-State Circuits, vol. 53, no. 12, pp. 3484–3496, Dec. 2018. [7] Y.-S. Shu, L.-T. Kuo, and T.-Y. Lo, “An Oversampling SAR ADC with DAC Mismatch Error Shaping Achieving 105 dB SFDR and 101 dB SNDR Over 1 kHz BW in 55 nm CMOS,” IEEE J. Solid-State Circuits, vol. 51, no. 12, pp. 2928–2940, Dec. 2016. [8] B. P. Ginsburg and A. P. Chandrakasan, “An Energy-Efficient Charge Recycling Approach for a SAR Converter with Capacitive DAC,” in Proc. IEEE Int. Symp. Circuits and Systems, May 2005, vol. 1, pp.184-187. [9] W. Liu, F. Y. Zhong, C. Zhong, and P. Y. Chiang, “Single-channel, 1.25-GS/s, 6-bit, Loop-Unrolled Asynchronous SAR-ADC in 40 nm-CMOS,” in Procs. IEEE Custom Integr. Circuits Conf., pp. 1–4, Sep. 2010. [10] C.-C. Liu, S.-J. Chang, G.-Y. Huang, Y.-Z. Lin, C.-M. Huang and C.-H. Huang, “A 10b 100MS/s 1.13mW SAR ADC with Binary Scaled Error Compensation,” in ISSCC Dig. Tech. Papers, Feb. 2010, pp. 386-387. [11] M. Gandara, W. Guo, X. Tang, L. Chen, Y. Yoon, and N. Sun, “A Pipelined SAR ADC Reusing the Comparator as Residue Amplifier,” in Proc. IEEE Custom Integr. Circuits Conf., Apr./May 2017, pp. 1–4. [12] G.-Y. Huang, S.-J. Chang, Y.-Z. Lin, C.-C. Liu, and C.- P. Huang, “A 10b 200MS/s 0.82mW SAR ADC in 40nm CMOS, ” in Proc. Asia Solid-State Circuits Conference., Nov. 2013, pp. 289-292. [13] C. C. Liu and M. C. Huang, “A 0.46 mW 5 MHz-BW 79.7 dB-SNDR Noise-Shaping SAR ADC with Dynamic-Amplifier-Based FIR-IIR Filter,” in ISSCC Dig. Tech. Papers, Feb. 2017, pp. 466–467. [14] W. Guo, H. Zhuang, and N. Sun, “A 13 b-ENOB 173 dB-FoM 2nd-Order NS SAR ADC with Passive Integrators,” in Proc. IEEE Symp. VLSI Circuits, Jun. 2017, pp. C236–C237. [15] Z. Chen, M. Miyahara, and A. Matsuzawa, “A 9.35-ENOB, 14.8 fJ/conv.-step Fully-Passive Noise-Shaping SAR ADC,” in Proc. IEEE Symp. VLSI Circuits, Jun. 2015, pp. C64–C65. [16] K. Obata, K. Matsukawa, T. Miki, Y. Tsukamoto, and K. Sushihara, “A 97.99 dB SNDR, 2 kHz BW, 37.1 μW Noise-Shaping SAR ADC with Dynamic Element Matching and Modulation Dither Effect,” in Proc. IEEE Symp. VLSI Circuits, Jun. 2016, pp. 1–2. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/21089 | - |
dc.description.abstract | 本論文提出一個具有具選擇性誤差調變及雜訊調變之十三位元六千四百萬取樣頻率連續漸進式類比數位轉換器,三階的雜訊調變由誤差回饋的架構來實現,其中量化誤差回饋的架構採用動態比較器來重複做為動態放大器以及被動有限脈衝響應來達成,而在非線性的部分,主要由電容式數位類比轉換器中的電容所造成,而選擇性誤差調變則改善了上述非線性的問題。本晶片使用台積電四十奈米互補式金屬氧化物半導體製程所實現,本晶片操作於六千四百萬取樣頻率,並於超取樣率為10.66下得到71 dB的訊號雜訊失真比,達到Schreier品質因素(FoM)為160 dB以及Walden品質因素為50fJ/conversion-step。在1.2伏特的電源供應下總共消耗869微瓦,晶片的核心面積小於0.03平方毫米。 | zh_TW |
dc.description.abstract | This thesis presents a 3rd-order noise-shaping successive-approximation register (SAR) ADC with selective mismatch error shaping. A 3rd-order noise shaping is achieved by implementing an error-feedback (EF) structure with comparator-reused dynamic amplifier and passive finite impulse response (FIR). The non-linearity resulting from capacitor mismatch is minimized by employing selective mismatch error shaping (MES). Fabricated in 40-nm CMOS, the prototype chip achieves a peak SNDR of 71 dB when operating at 64MS/s with an over-sampling ratio (OSR) of 10.66. The Schreier FoM is 160 dB, and the Walden FoM is 50 fJ/conversion-step. This chip occupies an active area smaller than 0.03 mm2 and consumes 869 μW with a 1.2-V supply. | en |
dc.description.provenance | Made available in DSpace on 2021-06-08T03:26:51Z (GMT). No. of bitstreams: 1 ntu-109-R04943046-1.pdf: 6747498 bytes, checksum: de1ef937fa20637b105d87a0bb01cc57 (MD5) Previous issue date: 2020 | en |
dc.description.tableofcontents | 致謝 i
摘要 ii Abstract iii Contents iv List of Figures vii List of Tables xi Chapter 1 Introduction_______________________________________________1 1.1 Motivation and Research Goals 1 1.2 Thesis Organization 2 Chapter 2 Fundamentals of ADCs______________________________________3 2.1 Introduction 3 2.2 ADC Performance Metrics 3 2.2.1 Differential and Integral Nonlinearity (DNL, INL) ............................ 3 2.2.2 Signal-to-Noise Ratio (SNR) ...6 2.2.3 Signal-to-Noise-and-Distortion Ratio (SNDR) 8 2.2.4 Effective Number-of-Bits (ENOB) 8 2.2.5 Spurious-Free Dynamic Range (SFDR) 8 2.2.6 Figure of Merit (FoM) 9 2.3 Architectures of Analog-to-Digital Converter 10 2.3.1 Flash ADC 10 2.3.2 Subrange ADC 11 2.3.3 Successive-Approximation Register ADC 12 2.3.4 Pipelined ADC 14 2.3.5 Time-Interleaved ADC 15 Chapter 3 Architectures of SAR ADC__________________________________17 3.1 Introduction 17 3.2 Conventional SAR ADC 17 3.3 Noise-Shaping Architectures 19 3.3.1 Cascaded Integrator Feed-Forward 22 3.3.2 Error Feedback 24 3.4 Mismatch Error Shaping 25 3.5 The proposed Architecture 29 Chapter 4 Circuit Implementation____________________________________35 4.1 Introduction 35 4.2 Proposed Architecture 35 4.3 Capacitive DAC 37 4.4 Bootstrapped Switch 43 4.5 Dynamic Comparator 46 4.6 Dynamic Amplifier 49 4.7 Internal Clock Generator and Data Register 51 4.8 Noise Analysis 55 4.9 Layout Floor Plan 58 4.10 Post-Layout Simulation 61 Chapter 5 Experimental Results______________________________________64 5.1 Introduction 64 5.2 Measurement Setup 65 5.3 Print Circuit Board Design 66 5.4 Measurement Results 67 5.5 Performance Summary 76 5.6 Conclusions and Future Works 78 Bibliography ………………………………………………………………………….79 | |
dc.language.iso | en | |
dc.title | 具選擇性誤差調變及雜訊調變之十三位元六千四百萬取樣頻率連續漸進式類比數位轉換器 | zh_TW |
dc.title | A 13-bit 64MS/s Noise-Shaping Successive-Approximation A/D Converter with Selective Mismatch Error Shaping | en |
dc.type | Thesis | |
dc.date.schoolyear | 108-1 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 劉深淵(Shen-Iuan Liu),陳信樹(Hsin-Shu Chen),謝志成(Chih-Cheng Hsieh),洪崇智(Chung-Chih Hung) | |
dc.subject.keyword | 類比數位轉換器,動態放大器,數位類比轉換器之誤差調變,雜訊調變,誤差回饋,超取樣類比數位轉換器,連續漸進式, | zh_TW |
dc.subject.keyword | Analog-to-digital converter (ADC),dynamic amplifier,DAC mismatch error shaping,noise shaping,error feedback (EF) structure,oversampling ADC,successive-approximation-register (SAR)., | en |
dc.relation.page | 80 | |
dc.identifier.doi | 10.6342/NTU202000152 | |
dc.rights.note | 未授權 | |
dc.date.accepted | 2020-01-17 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
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