應用於生醫系統之低功耗逐漸趨近式類比至數位轉換器之設計

Abstract

本篇論文提出兩個適用於逐漸趨近式類比至數位轉換器(SAR ADC)的類比及混合電路設計技術，並已經由晶片下線與量測結果驗證這些技術的實用性。 第一個技術是使用混合式的單位電容。基於先前的設計，本篇論文使用了兩種不同的單位電容，將10-bit 解析度之SAR ADC 提升至12-bit 。且由於前10-bit的電容陣列之容值大小並沒有隨之改變，因此相較於使用單一單位電容之電路架構，本技術並不會增加額外的晶片面積（小於1%），電容切換時的功耗也幾乎沒有增加。採用此技術的類比至數位轉換器在1伏特的操作電壓下，其量測之功率消耗為10.55μW，有效位元數為10.827 bits。其品質因數為29.0 fJ/conversion-step。 第二個技術是次階逐漸趨近式類比至數位轉換器。本技術在電路架構中加入了一個解析度較低的SAR ADC，用以預先得知前n個位元的粗略值，再經過一個判定切換可否省略的邏輯電路，來達到省電的效果。採用此技術的類比至數位轉換器在1伏特的操作電壓下，其模擬之功率消耗為3.683μW，有效位元數為11.818 bits。其品質因數為5.099 fJ/conversion-step。 此兩個設計都是在0.18μm 1P6M CMOS technology製作的。

This thesis presents two analog and mixed-signal circuit design techniques for successive-approximation register (SAR) analog-to-digital converters (ADCs). According to the measurement results of the experimental prototypes, the presented techniques are verified. The first technique is hybrid unit capacitors. Comparing to last work [1], the resolution bit has been enhanced by adding extra capacitor arrays with an additional smaller unit capacitor. This relevant prototype SAR ADC consumes 10.55μW at 1-V supply, and the effective number of bit (ENOB) is 10.827 bits. The resultant figure of merit (FoM) is 29.0 fJ/conversion-step by measurement results. The second technique is applying a sub-ranged SAR ADC. By adding a 5-bit sub-ranged SAR ADC to make a pre-decision of the first 5 bits, the switching power of system could be reduced by half. This relevant prototype SAR ADC consumes 3.683μW at 1-V supply, and the ENOB is 11.818 bits. The resultant FoM is 5.099 fJ/conversion-step by simulation results. Both of the prototypes are implemented in the 0.18μm 1P6M CMOS technology.