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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 呂學士 | |
| dc.contributor.author | Yen-Ting Wu | en |
| dc.contributor.author | 吳彥霆 | zh_TW |
| dc.date.accessioned | 2021-06-08T02:47:37Z | - |
| dc.date.copyright | 2017-08-24 | |
| dc.date.issued | 2017 | |
| dc.date.submitted | 2017-08-19 | |
| dc.identifier.citation | [1] C. Y. Chou, “Design of Low Power SAR Analog-to-Digital Converters for Biomedical System Applications, ” National Taiwan University MS Thesis, 2016.
[2] C. C, Liu, S. J. Chang, G. Y. Huang, and Y Z. Lin, 'A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure,' IEEE Journal of Solid-State Circuits, vol. 45, no. 4, pp. 731-740, Apr. 2010. [3] S. H. Cho, C. K. Lee, J. K. Kwon, and S. T. Ryu, 'A 550-µw 10-b 40-MS/s SAR ADC with Multistep Addition-Only Digital Error Correction,' IEEE Journal of Solid-State Circuits, vol. 46, no. 8, pp. 1881-1892, Aug. 2011. [4] T. C. Carusone, D. Johns, and K. Martin, Analog Integrated Circuit Design, John Wiley & Sons, Inc., 2012. [5] H. Y. Tai, Y. S. Hu, H. W. Chen, and H. S. Chen,' A 0.85fJ/conversion-step 10b 200kS/s Subranging SAR ADC in 40nm CMOS,ISSCC,' pp.196-197, Feb. 2014. [6] A. M. Abo, P. R. Gray, 'A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter,' IEEE Journal of Solid-State Circuits, vol. 34, no. 5, pp. 599-606, May 1999. [7] C. C. Liu, S. J. Chang, G. Y Huang, Y Z. Lin, C. M. Huang, C. H. Huang, L. Bu, and C. C. Tsai, 'A 10b IOOMS/s 1.13mW SAR ADC with Binary-Scaled Error Compensation,' in IEEE International Solid-State Circuits Conference Digest of Technical Papers, 2010, pp. 386–387. [8] H. W. Chang, “A Low Power Analog-to-Digital Converter for ECG Signal,” National Taiwan University MS Thesis, 2012. [9] P. H. Fang, “Design and Application of Low Power Pipelined and SAR,” National Taiwan University MS Thesis, 2009. [10] C. C. Liu, S. J. Chang, G. Y. Huang, and Y. Z. Lin, “A 0.92mW 10-bit 50-MS/s SAR ADC in 0.13 μm CMOS process,” in IEEE Symp. VLSI Circuits Dig., Jun. 2009, pp. 236–237. [11] S. W. M. Chen and R. W. Brodersen, “A 6-bit 600-MS/s 5.3-mW Asynchronous ADC in 0.13-um CMOS,” IEEE Journal of Solid-State Circuit, pp. 2669-2680, Dec. 2006. [12] B. Razavi, Principles of Data Conversion System Design, IEEE Press, 1995. [13] B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill, 2001. [14] J. Y. Lin and C. C. Hsieh, 'A 0.3 V 10-bit 1.17 f SAR ADC with Merge and Split Switching in 90 nm CMOS,' IEEE Transactions on Circuits and Systems I, vol. 62, no. 1, pp. 70-79, Jan. 2015. [15] G. Y. Huang, S. J. Chang, C. C. Liu, and Y. Z. Lin, 'A 1-µW 10-bit 200-kS/s SAR ADC With a Bypass Window for Biomedical Applications,' IEEE Journal of Solid-State Circuits, vol. 47, no. 11, pp. 2783-2795, Nov. 2012. [16] C. C. Liu, C. H. Kuo, Y. Z. Lin, 'A 10 bit 320 MS/s Low-Cost SAR ADC for IEEE 802.11ac Applications in 20 nm CMOS,' IEEE Journal of Solid-State Circuits, vol. 50, no. 11, pp. 2645-2654, Nov 2015. [17] B. P. Ginsburg and A. P. Chandrakasan, '500-MS/s 5-bit ADC in 65-nm CMOS With Split Capacitor Array DAC,' IEEE Journal of Solid-State Circuits, vol. 42, no. 4, pp. 739 - 747, Apr. 2007. [18] V. Hariprasath, J. Guerber, S. -H. Lee, and U. -K. Moon, 'Merged capacitor switching based SAR ADC with highest switching energy-efficiency,' Electronics Letters, vol. 46, no. 9, pp. 620 - 621, Apr. 2010. [19] B. P. Ginsburg and A. P. Chandrakasan, “An energy-efficient charge recycling approach for a SAR converter with capacitive DAC,” in Proc. IEEE Int. Symp. Circuits and Systems, 2005, vol. 1, pp. 184–187. [20] B. Wicht, T. Nirschl, and D. Schmitt-Landsiedel, 'Yield and speed optimization of a latch-type voltage sense amplifier,' IEEE Journal of Solid-State Circuits, vol. 39, no. 7, pp. 1148 - 1158, Jul. 2004. [21] Samaneh Babayan-Mashhadi, and Reza Lotfi, 'Analysis and Design of a Low-Voltage Low-Power Double-Tail Comparator,' IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 22, no. 2, pp. 343-352. [22] Jun He; Sanyi Zhan, Degang Chen, and Randall L. Geiger, 'Analyses of Static and Dynamic Random Offset Voltages in Dynamic Comparators,' IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 56, no. 5, pp. 911-919, May 2009. [23] Bernhard Goll, and Horst Zimmermann, 'A Comparator with Reduced Delay Time in 65-nm CMOS for Supply Voltages Down to 0.65 V,' IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 56, no. 11, pp. 810-814, Nov. 2009. [24] Y.-C. Lien, 'A 4.5-mW 8-b 750-MS/s 2-b/step asynchronous subranged SAR ADC in 28-nm CMOS technology,' in Symposium on VLSI Circuits (VLSIC), Honolulu, HI, 2012. [25] Pierluigi Nuzzo, Fernando De Bernardinis, Pierangelo Terreni, and Geert Van der Plas, 'Noise Analysis of Regenerative Comparators for Reconfigurable ADC Architectures,' IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 55, no. 6, pp. 1441-1454, Jul. 2008. [26] F. Kuttner, “A 1.2-V 10-b 20-Msample/s nonbinary successive approximation ADC in 0.13-μm CMOS,” ISSCC Dig. Tech. Papers, pp. 176-177, Feb., 2002. [27] Bernhard Goll, and Horst Zimmermann, 'A 0.12μm CMOS Comparator Requiring 0.5V at 600MHz and 1.5V at 6GHz,' in IEEE International Solid-State Circuits Conference. Digest of Technical Papers, 2007. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/20404 | - |
| dc.description.abstract | 本篇論文提出兩個適用於逐漸趨近式類比至數位轉換器(SAR ADC)的類比及混合電路設計技術，並已經由晶片下線與量測結果驗證這些技術的實用性。
第一個技術是使用混合式的單位電容。基於先前的設計，本篇論文使用了兩種不同的單位電容，將10-bit 解析度之SAR ADC 提升至12-bit 。且由於前10-bit的電容陣列之容值大小並沒有隨之改變，因此相較於使用單一單位電容之電路架構，本技術並不會增加額外的晶片面積（小於1%），電容切換時的功耗也幾乎沒有增加。採用此技術的類比至數位轉換器在1伏特的操作電壓下，其量測之功率消耗為10.55μW，有效位元數為10.827 bits。其品質因數為29.0 fJ/conversion-step。 第二個技術是次階逐漸趨近式類比至數位轉換器。本技術在電路架構中加入了一個解析度較低的SAR ADC，用以預先得知前n個位元的粗略值，再經過一個判定切換可否省略的邏輯電路，來達到省電的效果。採用此技術的類比至數位轉換器在1伏特的操作電壓下，其模擬之功率消耗為3.683μW，有效位元數為11.818 bits。其品質因數為5.099 fJ/conversion-step。 此兩個設計都是在0.18μm 1P6M CMOS technology製作的。 | zh_TW |
| dc.description.abstract | This thesis presents two analog and mixed-signal circuit design techniques for successive-approximation register (SAR) analog-to-digital converters (ADCs). According to the measurement results of the experimental prototypes, the presented techniques are verified.
The first technique is hybrid unit capacitors. Comparing to last work [1], the resolution bit has been enhanced by adding extra capacitor arrays with an additional smaller unit capacitor. This relevant prototype SAR ADC consumes 10.55μW at 1-V supply, and the effective number of bit (ENOB) is 10.827 bits. The resultant figure of merit (FoM) is 29.0 fJ/conversion-step by measurement results. The second technique is applying a sub-ranged SAR ADC. By adding a 5-bit sub-ranged SAR ADC to make a pre-decision of the first 5 bits, the switching power of system could be reduced by half. This relevant prototype SAR ADC consumes 3.683μW at 1-V supply, and the ENOB is 11.818 bits. The resultant FoM is 5.099 fJ/conversion-step by simulation results. Both of the prototypes are implemented in the 0.18μm 1P6M CMOS technology. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-08T02:47:37Z (GMT). No. of bitstreams: 1 ntu-106-R04943127-1.pdf: 3486291 bytes, checksum: 46289bc3989990a5fd97f748ffb7fd16 (MD5) Previous issue date: 2017 | en |
| dc.description.tableofcontents | 口試委員審定書 i
誌謝 ii 中文摘要 iii ABSTRACT iv CONTENTS vi List of Figures x List of Tables xv Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Thesis Organization 2 Chapter 2 The Fundamentals of Analog-to-Digital Converters 3 2.1 Introduction 3 2.2 Performance evaluation parameters 4 2.2.1 Resolution 4 2.2.2 Offset Error and Gain Error 4 2.2.3 Differential Nonlinearity （DNL） 5 2.2.4 Integral Nonlinearity（INL） 6 2.2.5 Signal-to-Noise Ratio（SNR） 7 2.2.6 Signal-to-Noise and Distortion Ratio（SNDR） 7 2.2.7 Effective Number of Bits（ENOB） 7 2.2.8 Total Harmonic Distortion（THD） 8 2.2.9 Spurious Free Dynamic Range（SFDR） 8 2.2.10 Dynamic Range（DR） 9 2.2.11 Figure of Merit（FoM） 10 2.3 ADC Architectures 11 2.3.1 Flash ADC 11 2.3.2 Pipeline ADC 12 2.3.3 Successive Approximation Register ADC 13 2.3.4 Delta-Sigma ADC 14 2.3.5 Comparison of the ADCs 15 Chapter 3 A 1V, 12-bits, Low Power SAR ADC with Hybrid Unit Capacitors 17 3.1 Introduction 17 3.2 SAR ADC Architecture 18 3.2.1 Basic Operation of Asynchronous SAR ADC 18 3.2.2 Hybrid Capacitor Arrays 25 3.2.3 Digital Error Correction 27 3.2.4 Circuit Implementation 31 3.3 Building Blocks Implementation 35 3.3.1 Sample and Hold Circuit 35 3.3.2 Capacitor Array 42 3.3.3 Dynamic Comparator 46 3.3.4 SAR Control Logic 51 3.3.5 Digital Error Correction Logic 55 3.4 SAR ADC Simulation 57 3.4.1 Function Simulation 57 3.4.2 Dynamic Performance Simulation 58 3.4.3 Static Performance Simulation 61 3.5 Measurement Results 66 3.5.1 The PCB Design 68 3.5.2 Measurement Setup 71 3.5.3 Static Performance Measurement 73 3.5.4 Dynamic Performance Measurement 75 3.5.5 Performance Metric 76 Chapter 4 A 1V, 12-bits, Sub-Ranged SAR ADC with Hybrid Unit Capacitor 78 4.1 Introduction 78 4.2 Skipping Scenario of Switching Process 79 4.3 A Coarse ADC Applied 12-bits SAR ADC 81 4.4 SAR ADC Architecture 83 4.4.1 Circuit Implementation 83 4.4.2 SAR ADC Simulation 87 4.4.3 Measurement Results 91 Chapter 5 Conclusions 95 References 96 | |
| dc.language.iso | en | |
| dc.title | 應用於生醫系統之低功耗逐漸趨近式類比至數位轉換器之設計 | zh_TW |
| dc.title | Design of Low Power SAR Analog-to-Digital Converters for Biomedical System Applications | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 105-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 孫台平,孟慶宗,彭盛裕 | |
| dc.subject.keyword | 逐漸趨近式,類比至數位轉換器,數位錯誤補償,混合式單位電容,次階逐漸趨近式類比至數位轉換器, | zh_TW |
| dc.subject.keyword | successive-approximation register,analog-to-digital converters,digital error correction,hybrid unit capacitor,sub-ranged SAR ADC, | en |
| dc.relation.page | 100 | |
| dc.identifier.doi | 10.6342/NTU201703507 | |
| dc.rights.note | 未授權 | |
| dc.date.accepted | 2017-08-20 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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