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標題: | 用於無線電力監控應用之類比前端讀取電路 Analog Front-End Readout Circuits for Wireless Power-Line Monitoring Application |
作者: | Chi-Yin Hsieh 謝其穎 |
指導教授: | 呂良鴻 |
關鍵字: | 類比前端,電容耦合式放大器,截波穩定,循續漸近式類比數位轉換器,線性穩壓器, analog front-end,capacitively-coupled amplifier,chopper stabilization,SAR ADC,LDO, |
出版年 : | 2018 |
學位: | 碩士 |
摘要: | 隨著現代社會家用電器和電子設備數量的爆炸性增長,家用電器安全已成為一個重要課題。而藉由由多個無線傳感器節點構成了無線傳感器網絡的概念,若將所有家用電器視為個別的無線傳感器節點,並且這些無線傳感器節點都連接到同一個監控中心,本論文提出了一個無線電力線監測傳感器單元的應用。而本論文將著重在介紹該無線電力線監測傳感器單元的類比前端讀取電路部分。整個類比前端讀取系統是由一個雙通道類比前端放大器、一個類比多工器、一個同步逐次逼近暫存器類比數位轉換器和兩個線性低壓差穩壓器所組成。其中,雙通道類比前端放大器又是由斬波穩定電容耦合放大器和主動RC低通濾波器所組成。本論文將分別詳細介紹每個電路區塊。而最後,一個類比前端讀取SoC將透過0.18μm CMOS工藝製造並驗證。此類比前端讀取SoC在1.6V的供應電壓下共消耗54μA的電流,並達到61.7~81.6dB的電壓增益和一組250-kbps,44.69dB SNDR的數位資料輸出。 With the explosive growth on the number of household appliances and electronic equipment in modern society, household electrical safety has become an important issue. Followed by the concept of wireless sensor networks consisting of several wireless sensor nodes, by treating all of the related household electrical appliances as wireless sensor nodes and all of these wireless sensor nodes are connected to a fully integrated central monitoring system, a wireless power-line monitoring sensor unit is proposed as an application. This thesis presents and focuses on the analog front-end readout circuits for this wireless power-line monitoring sensor unit. The entire front-end readout system consists of a 2-channel front-end amplifier, an analog multiplexer, a synchronous successive approximation register analog-to-digital converter, and two on-chip linear low-dropout regulators. Among them, the 2-channel front-end amplifier is further composed of chopper-stabilized capacitively-coupled amplifiers and active-RC low-pass filters. Detailed introductions of each building block will be presented in the thesis respectively. Finally, an analog front-end readout SoC is fabricated in 0.18-μm CMOS process for system integration. Drawing a dc current of 54 μA from a nominal 1.6-V power supply, the fabricated analog front-end readout SoC exhibits 61.7 ~ 81.6 dB voltage gains under 4 different non-uniform control steps and streams 250-kbps serial digitized data that can achieve 44.69 dB SNDR. |
URI: | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/20262 |
DOI: | 10.6342/NTU201800188 |
全文授權: | 未授權 |
顯示於系所單位: | 電機工程學系 |
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ntu-107-1.pdf 目前未授權公開取用 | 4.41 MB | Adobe PDF |
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