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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 呂良鴻 | |
dc.contributor.author | Chi-Yin Hsieh | en |
dc.contributor.author | 謝其穎 | zh_TW |
dc.date.accessioned | 2021-06-08T02:43:33Z | - |
dc.date.copyright | 2018-02-23 | |
dc.date.issued | 2018 | |
dc.date.submitted | 2018-01-26 | |
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dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/20262 | - |
dc.description.abstract | 隨著現代社會家用電器和電子設備數量的爆炸性增長,家用電器安全已成為一個重要課題。而藉由由多個無線傳感器節點構成了無線傳感器網絡的概念,若將所有家用電器視為個別的無線傳感器節點,並且這些無線傳感器節點都連接到同一個監控中心,本論文提出了一個無線電力線監測傳感器單元的應用。而本論文將著重在介紹該無線電力線監測傳感器單元的類比前端讀取電路部分。整個類比前端讀取系統是由一個雙通道類比前端放大器、一個類比多工器、一個同步逐次逼近暫存器類比數位轉換器和兩個線性低壓差穩壓器所組成。其中,雙通道類比前端放大器又是由斬波穩定電容耦合放大器和主動RC低通濾波器所組成。本論文將分別詳細介紹每個電路區塊。而最後,一個類比前端讀取SoC將透過0.18μm CMOS工藝製造並驗證。此類比前端讀取SoC在1.6V的供應電壓下共消耗54μA的電流,並達到61.7~81.6dB的電壓增益和一組250-kbps,44.69dB SNDR的數位資料輸出。 | zh_TW |
dc.description.abstract | With the explosive growth on the number of household appliances and electronic equipment in modern society, household electrical safety has become an important issue. Followed by the concept of wireless sensor networks consisting of several wireless sensor nodes, by treating all of the related household electrical appliances as wireless sensor nodes and all of these wireless sensor nodes are connected to a fully integrated central monitoring system, a wireless power-line monitoring sensor unit is proposed as an application. This thesis presents and focuses on the analog front-end readout circuits for this wireless power-line monitoring sensor unit. The entire front-end readout system consists of a 2-channel front-end amplifier, an analog multiplexer, a synchronous successive approximation register analog-to-digital converter, and two on-chip linear low-dropout regulators. Among them, the 2-channel front-end amplifier is further composed of chopper-stabilized capacitively-coupled amplifiers and active-RC low-pass filters. Detailed introductions of each building block will be presented in the thesis respectively. Finally, an analog front-end readout SoC is fabricated in 0.18-μm CMOS process for system integration. Drawing a dc current of 54 μA from a nominal 1.6-V power supply, the fabricated analog front-end readout SoC exhibits 61.7 ~ 81.6 dB voltage gains under 4 different non-uniform control steps and streams 250-kbps serial digitized data that can achieve 44.69 dB SNDR. | en |
dc.description.provenance | Made available in DSpace on 2021-06-08T02:43:33Z (GMT). No. of bitstreams: 1 ntu-107-R03943115-1.pdf: 4516630 bytes, checksum: cd1e7e2fa6cdc62611e8afed37cdfcb1 (MD5) Previous issue date: 2018 | en |
dc.description.tableofcontents | 口試委員會審定書 i
致謝 v 摘要 vii Abstract ix Contents xi List of Figures xv List of Tables xix Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Thesis Organization 3 Chapter 2 Background 5 2.1 Recent Development of Power Monitoring 5 2.2 Overview of Wireless Power-Line Monitoring 7 2.3 Design Specification of the Proposed Front-End Readout Circuit 10 2.3.1 Design Parameters of the Chopper-Stabilized Capacitively-Coupled Amplifier 11 2.3.2 Design Parameters of the Active-RC Low-Pass Filter 12 2.3.3 Design Parameters of the SAR Analog-to-Digital Converter 12 Chapter 3 A Chopper-Stabilized Capacitively-Coupled Amplifier 15 3.1 Introduction 15 3.2 Proposed Architecture 16 3.3 Circuit Implementation 17 3.3.1 Chopper Stabilization Technique 17 3.3.2 Capacitively-Coupled Amplifier 20 3.3.3 Chopper Switches Placement 25 3.3.4 Active-RC Low-Pass Filter 27 3.4 Experimental Results 30 3.4.1 Chopper-Stabilized Capacitively-Coupled Amplifier 30 3.4.2 Active-RC Low-Pass Filter 34 3.5 Summary 35 Chapter 4 An 8-bit Synchronous SAR Analog-to-Digital Converter 37 4.1 Introduction 37 4.2 Proposed Architecture 38 4.3 Circuit Implementation 41 4.3.1 Sample-and-Hold Circuit 41 4.3.2 Capacitive DAC 42 4.3.3 Dynamic Latch Comparator 44 4.3.4 SAR Control Logic 45 4.3.5 Voltage Level Shifter 47 4.4 Experimental Results 48 4.5 Summary 52 Chapter 5 A Linear Low-Dropout Regulator 53 5.1 Introduction 53 5.2 Circuit Implementation 55 5.2.1 Linear Low-Dropout Regulator 55 5.2.2 Reference Generator 58 5.3 Experimental Results 60 5.4 Summary 63 Chapter 6 An Analog Front-End Readout SoC 65 6.1 Introduction 65 6.2 System Overview 66 6.3 Peripheral Circuits 68 6.3.1 Analog Multiplexer 68 6.3.2 Chopper Clock Generator 70 6.4 Experimental Results 72 6.5 Summary 78 Chapter 7 Conclusion 79 Bibliography 83 | |
dc.language.iso | en | |
dc.title | 用於無線電力監控應用之類比前端讀取電路 | zh_TW |
dc.title | Analog Front-End Readout Circuits for Wireless Power-Line Monitoring Application | en |
dc.type | Thesis | |
dc.date.schoolyear | 106-1 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 林宗賢,黃俊郎 | |
dc.subject.keyword | 類比前端,電容耦合式放大器,截波穩定,循續漸近式類比數位轉換器,線性穩壓器, | zh_TW |
dc.subject.keyword | analog front-end,capacitively-coupled amplifier,chopper stabilization,SAR ADC,LDO, | en |
dc.relation.page | 86 | |
dc.identifier.doi | 10.6342/NTU201800188 | |
dc.rights.note | 未授權 | |
dc.date.accepted | 2018-01-26 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電機工程學研究所 | zh_TW |
顯示於系所單位: | 電機工程學系 |
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