以CMOS製程之接收信號強度指示電路設計

Abstract

此論文研究使用連續檢測對數放大器架構設計接收信號強度指示電路，使用製程為TSMC 0.18μm CMOS製程和TSMC 40nm CMOS製程。其中連續檢測對數放大器架構是由限制放大器、非對稱源極耦合差動對和低通濾波器組成。在0.18μm CMOS製程下量測結果在0.1GHz到1GHz之間約有38dB的動態範圍，在1GHz到2GHz之間約有30dB的動態範圍功率，消耗為22.45mW，晶片面積為0.28 。在40nm CMOS製程下模擬結果在0.1GHz到2.5GHz之間約有40dB的動態範圍，功率消耗為7.66mW，晶片面積為0.06 mm2。

This thesis designs received signal strength indicator circuits (RSSI) by using successive detection logarithmic amplifier (SDLA) topology under TSMC 0.18μm and 40nm CMOS technology. Successive detection logarithmic amplifier composes of limiting amplifier, unbalanced source-coupled differential pair and low-pass filter. In design using 0.18μm CMOS process, the measurement results show that dynamic range of about 38dB from 0.1GHz to 1GHz, and dynamic range of 30dB from 1GHz to 2GHz. DC power consumption is 22.45mW, and chip size is 0.28 . In 40-nm CMOS process, the stimulation results show dynamic range with 40dB from 0.1GHz to 2.5GHz, and DC power consumption is 7.66mW with chip size of 0.06 mm2.