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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 盧信嘉(Hsin-Chia Lu) | |
dc.contributor.author | Chao-Wei Huang | en |
dc.contributor.author | 黃朝偉 | zh_TW |
dc.date.accessioned | 2021-06-08T01:42:37Z | - |
dc.date.copyright | 2016-08-30 | |
dc.date.issued | 2016 | |
dc.date.submitted | 2016-08-17 | |
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[11] Janne-Wha Wu, Sheng-Wen Chen, Ching-Wen Tang and Ming-Guang Chen, “Closed-loop power control of radio frequency power amplifier module with an on-chip embedded power detector,” in 2006 of Asia-Pacific Microwave Conference, Dec. 2006, pp. 711-713. [12] Kazuya Yamamoto, Mitsubishi Miyashita, Hitoshi Kurusu, Nobuyuki Ogawa and Teruyuki Shimura, “A current-mirror-based GaAs-HBT RF power detector for wireless applications,” in IEEE Compound Semiconductor Integrated Circuit Symposium , pp.44-47, Oct. 2006. [13] Behzad. Razavi, Fundamental of Microelectronics, New York: McGraw-Hill, 2013. [14] LTC5507二極體偵測器http://cds.linear.com/docs/en/datasheet/5507f.pdf [15] Chris D. Holdenried, James W. Haslett, John G. McRory R. Douglas Beards and A. J. Bergsm, “A DC–4-GHz true logarithmic amplifier: theory and implementation,” IEEE Journal of Solid-State Circuits, vol. 37, no. 10, October 2002. [16] Richard Smith Hughes, Logarithmic Amplification with application to Radar and EW, Artech House, 1986. [17] Peter Chadwick, “Advances in logarithmic amplifiers,” in Proc. of 5th International Conference on Radio Receivers and Associated Systems, pp.51-58, Dec. 1990. [18] Behzad Razavi, Design of integrated circuits for optical communications, New York: McGraw-Hill, 2002. [19] Eduard. Säckinger and Wilhelm Fischer, “A 3-GHz 32-dB CMOS limiting amplifier for sonet OC-48 receiver,” IEEE J. Solid-State Circuits, vol. 35, no. 12, pp. 1884–1888, Dec. 2000. [20] Chia-Hsin Wu, Chang-Shun Liu, and Shen-Luan Liu, “A 2 GHz CMOS variable-gain amplifier with 50-dB linear-in-magnitude controlled gain range for 10 GBase-LX4 Ethernet,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2004, pp. 484–485. [21] Chia-Hsin Wu, Jieh-Wei Liao, and Shen-Luan Liu, “A 1V 4.2mW fully integrated 2.5 Gb/s CMOS limiting amplifier using folded active inductors,” in Proc. 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Haslett, “Modified CMOS Cherry-Hooper amplifiers with source follower feedback in 0.35μm technology,” 29th European Solid-State Circuit Conferences,pp.553-556, September 2003. [27] Paul R. Gray and Robert. G. Meyer, Analysis and Design of Analog Integrated Circuits, 4th edition. New York: Wiley, 2001. [28] K. Kimura, “A unified analysis of four-quadrant analog multipliers consisting of emitter and source coupled transistors operable on low supply voltage,” IEICE Trans. Electron., vol. E76-C, no. 5, pp46-45.May 1993. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/19023 | - |
dc.description.abstract | 此論文研究使用連續檢測對數放大器架構設計接收信號強度指示電路,使用製程為TSMC 0.18μm CMOS製程和TSMC 40nm CMOS製程。其中連續檢測對數放大器架構是由限制放大器、非對稱源極耦合差動對和低通濾波器組成。在0.18μm CMOS製程下量測結果在0.1GHz到1GHz之間約有38dB的動態範圍,在1GHz到2GHz之間約有30dB的動態範圍功率,消耗為22.45mW,晶片面積為0.28 。在40nm CMOS製程下模擬結果在0.1GHz到2.5GHz之間約有40dB的動態範圍,功率消耗為7.66mW,晶片面積為0.06 mm2。 | zh_TW |
dc.description.abstract | This thesis designs received signal strength indicator circuits (RSSI) by using successive detection logarithmic amplifier (SDLA) topology under TSMC 0.18μm and 40nm CMOS technology. Successive detection logarithmic amplifier composes of limiting amplifier, unbalanced source-coupled differential pair and low-pass filter. In design using 0.18μm CMOS process, the measurement results show that dynamic range of about 38dB from 0.1GHz to 1GHz, and dynamic range of 30dB from 1GHz to 2GHz. DC power consumption is 22.45mW, and chip size is 0.28 . In 40-nm CMOS process, the stimulation results show dynamic range with 40dB from 0.1GHz to 2.5GHz, and DC power consumption is 7.66mW with chip size of 0.06 mm2. | en |
dc.description.provenance | Made available in DSpace on 2021-06-08T01:42:37Z (GMT). No. of bitstreams: 1 ntu-105-R03943129-1.pdf: 6154321 bytes, checksum: 57dbf2fd78f8c5767be004bec4c10f54 (MD5) Previous issue date: 2016 | en |
dc.description.tableofcontents | 口試委員會審定書 #
誌謝 i 中文摘要 ii ABSTRACT iii CONTENTS iv LIST OF FIGURES vii LIST OF TABLES xi Chapter 1 簡介 1 1.1 動機 1 1.2 文獻回顧 2 1.3 各章節簡介 5 Chapter 2 對數放大器 6 2.1 二極體偵測器[11][12] 6 2.2 真對數放大器(True Logarithmic Amplifier) 8 2.3 理想對數轉移函數 10 2.3.1 理想對數轉移函數 10 2.3.2 BJT負載放大器 13 2.3.3 連續偵測放大器[17] 14 2.4 規格定義與考量[16] 20 2.4.1 頻率範圍(frequency range) 20 2.4.2 動態範圍(dynamic range) 20 2.4.3 對數斜率(logarithmic slope) 20 2.4.4 直流電壓輸出偏移(output DC offset) 20 2.4.5 溫度變異(temperature variation) 20 Chapter 3 限制放大器[18] 21 3.1 共源級放大器 21 3.1.1 電阻負載之共源級放大器 21 3.1.2 主動負載之共源級放大器 22 3.2 電感負載性限制放大器[19] 23 3.3 主動電感[20][21] 27 3.4 轉阻放大器[23][24] 28 3.5 Cherry-Hooper 放大器[25] 35 3.6 源極退化電容 42 Chapter 4 整流器電路 44 4.1 差動放大器[27] 44 4.2 半波整流器[28] 46 4.3 全波整流器[28] 49 Chapter 5 電路設計與量測結果 52 5.1 使用CMOS 0.18um製程的接收信號強度指示電路 52 5.2 量測結果 67 5.2.1 量測環境 67 5.3 使用CMOS 40nm製程的接收信號強度指示電路 73 Chapter 6 結論 82 參考文獻 84 | |
dc.language.iso | zh-TW | |
dc.title | 以CMOS製程之接收信號強度指示電路設計 | zh_TW |
dc.title | Design of Received Signal Strength Indicator Circuit
in CMOS Process | en |
dc.type | Thesis | |
dc.date.schoolyear | 104-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 林坤佑(Kun-You Lin),盧奕璋(Yi-Chang Lu),陳信樹(Hsin-Shu Chen) | |
dc.subject.keyword | 接受信號強度電路,連續檢測對數放大器,限制放大器,非對稱源極耦合差動對, | zh_TW |
dc.subject.keyword | received signal strength indicator circuit,successive detection logarithmic amplifier,limiting amplifier,unbalanced source-coupled differential pairs, | en |
dc.relation.page | 85 | |
dc.identifier.doi | 10.6342/NTU201603005 | |
dc.rights.note | 未授權 | |
dc.date.accepted | 2016-08-18 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
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