在速掃描鏈測試中速度路徑診斷之改良

Abstract

在評斷高效能的超大型積體電路 (VLSI) 產品時，工作模式時的時脈速度已成為重要的品質依據。如何不斷的改良設計以便將時脈加速是設計時極重要的一部分。在改良設計的循環過程中，是否能有效的偵測出限制整體時脈的速度路徑 (Speed-path) 扮演著關鍵的角色。隨著製程不斷進步，電晶體的密度越來越高的情勢下，如何從所有被在速測試圖樣激發的路徑中找出速度路徑已變得越來越有挑戰性。 本論文使用前人所提出的理論，先找出一群速度路徑候選者的集合。此集合已被證明包含所有真正的速度路徑。一開始我們會藉由觀察速度路徑間的關係，延伸出一套確定可以找到速度路徑的理論與實作方法。對於其他含有不確定性的路徑群，我們將提出一套以布林表示式表達此路徑群之間的邏輯關係的新理論。此布林表示式提供所有可能的組合情況來解釋這些路徑如何限制了整體的時脈。藉由處理這些表示式，我們可以大量的刪除不可能限制整體時脈的候選者。最後將確定的速度路徑與篩選過後的速度路徑候選群回饋給除錯工程師，可以減輕工程師們的負擔，加速改良設計的循環過程。

The operating clock frequency is an important performance metric of a high performance VLSI (very large-scale integration) product. Pushing clock frequency to a higher level through several design iterations (or design stepping) has become an important part of design process. In design stepping, speed-path is the path that limits the performance of a chip. The speed-path has different definition from critical path. Critical path is the path with longest delay in the nominal design, whereas there can be many speed-paths after manufacturing. The speed-path identification plays a critical role for design performance optimization. However, as the chip density keeps growing, it becomes challenging to find speed-paths of one chip from all sensitized paths with at-speed scan test patterns.

In this work, we use the method in [1] to generate an initial speed-path candidate (or suspect) set which has been proved to contain all real speed-paths. At first we derive a methodology to find conclusive speed-path by observing the relationship between the speed-path suspects. Then for the other speed-paths suspects called inconclusive speed-paths, we use a novel Boolean expression algorithm to provide a solution set for all possible combinations that describe the observed failing bits. By dealing with these Boolean expressions, we can remove fake speed-paths that cannot result in errors on the output. Finally we can feedback the conclusive speed-path and the remaining speed-paths to debug engineer to do design fix and performance optimization.