請用此 Handle URI 來引用此文件:
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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 黃俊郎(Jiun-Lang Huang) | |
dc.contributor.author | Yu-Ping Liu | en |
dc.contributor.author | 劉裕平 | zh_TW |
dc.date.accessioned | 2021-06-07T17:53:19Z | - |
dc.date.copyright | 2012-08-20 | |
dc.date.issued | 2012 | |
dc.date.submitted | 2012-08-17 | |
dc.identifier.citation | Bibliography
[1] Ruifeng Guo, W.-T. Cheng, K.-H. Tsai, “Speed-Path Debug Using At-Speed Scan Test Patterns”, European Test Symposium, 2009, pp.11-16. [2] K. Killpack, S. Natarajan, A. Krichnamachary, P. Bastani,“Case Study on Speed Failure Causes in a Microprocessor”, IEEE Design & Test of Computers, 2008, pp.224-230. [3] D. Josephson, “The Manic Depression of Microprocessor Debug”, Proc. ITC, 2002, pp. 657-663. [4] B. Vermeulen, S. Kumar Goel, “Design for Debug: Catching Design Errors in Digital Chips”, IEEE Design & Test of Comp., 2002, pp. 37-45. [5] M. Riley, N. Chelstrom, M. Genden, S. Sawamura, “Debug of CELL Processor: Moving the Lab into Silicon“, Proc. ITC, 2006, paper 26.1, pp.1-9. [6] L. M. Huisman, “Diagnosing Arbitrary Defects in Logic Designs Using Single Location at a Time (SLAT),” IEEE Tran. On CAD, 2004, pp. 91-101. [7] G.L. Smith, “Method for Delay Faults Based upon Paths,” Proc. ITC, 1985, pp. 342-349. [8] P. Pant, Y.-C. Hsu, S. K. Gupta, and A. Chatterjee, “Path Delay Fault Diagnosis in Combinational Circuits with Implicit Fault Enumeration”, IEEE Trans. on CAD, 2001, pp. 1226-1235. [9] P. Girard, C. Landrault, S. Pravossoudovitch, “A Novel Approach to Delay-Fault Diagnosis”, Proc. Design Automation Conference, 1992, pp. 357-360. [10] P. Girard, C. Landrault, S. Pravossoudovitch, “Delay-Fault Diagnosis Based on Critical Path Tracing from Symbolic Simulation”, IEEE Design and Test of Computers, Oct. 1992, pp. 1133-1136. [11] W.-T. Cheng, et al. “Enhancing Transition Fault Model for Delay Defect Diagnosis”, Proc. ATS, 2008, pp. 179-184. [12] K. Killpack, C. Kashyap, E. Chiprout, “Silicon Speedpath Measurement and Feedback into EDA flows”, Design Automation Conference, 2007, pp.390-395. [13] Li-C. Wang, T.M. Mak, K.-T. Cheng, M.S. Abadir, “On Path-Based Learning And Its Applications In Delay Test And Diagnosis”, Design Automation Conference, 2004, pp.492-497. [14] Li-C. Wang, “Data Learning Based Diagnosis”, Asia and South Pacific Design Automation Conference, 2010, pp.247-254. [15] P. Bastani, K. Killpack, Li-C. Wang, E. Chiprout, “Speedpath Prediction Based on Learning from a Small Set of Examples”, Design Automation Conference, 2008, pp.217-222. [16] P. Bastani, N. Callegari1, Li-C. Wang1, M.S. Abadir, “Diagnosis of design-silicon timing mismatch with feature encoding and importance ranking”, Proc. ITC, 2008, pp.1-10. [17] N. Callegari1, Li-C. Wang1, P. Bastani, “Feature based similarity search with application to speedpath analysis”, Proc. ITC, 2009, pp.1-10. [18] P. Bastani, N. Callegari, Li-C. Wang, M.S. Abadir, “Feature-Ranking Methodology to Diagnose Design-Silicon Timing Mismatch”, Design & Test of Computers, IEEE, 2010, p42-53. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/15839 | - |
dc.description.abstract | 在評斷高效能的超大型積體電路 (VLSI) 產品時,工作模式時的時脈速度已成為重要的品質依據。如何不斷的改良設計以便將時脈加速是設計時極重要的一部分。在改良設計的循環過程中,是否能有效的偵測出限制整體時脈的速度路徑 (Speed-path) 扮演著關鍵的角色。隨著製程不斷進步,電晶體的密度越來越高的情勢下,如何從所有被在速測試圖樣激發的路徑中找出速度路徑已變得越來越有挑戰性。
本論文使用前人所提出的理論,先找出一群速度路徑候選者的集合。此集合已被證明包含所有真正的速度路徑。一開始我們會藉由觀察速度路徑間的關係,延伸出一套確定可以找到速度路徑的理論與實作方法。對於其他含有不確定性的路徑群,我們將提出一套以布林表示式表達此路徑群之間的邏輯關係的新理論。此布林表示式提供所有可能的組合情況來解釋這些路徑如何限制了整體的時脈。藉由處理這些表示式,我們可以大量的刪除不可能限制整體時脈的候選者。最後將確定的速度路徑與篩選過後的速度路徑候選群回饋給除錯工程師,可以減輕工程師們的負擔,加速改良設計的循環過程。 | zh_TW |
dc.description.abstract | The operating clock frequency is an important performance metric of a high performance VLSI (very large-scale integration) product. Pushing clock frequency to a higher level through several design iterations (or design stepping) has become an important part of design process. In design stepping, speed-path is the path that limits the performance of a chip. The speed-path has different definition from critical path. Critical path is the path with longest delay in the nominal design, whereas there can be many speed-paths after manufacturing. The speed-path identification plays a critical role for design performance optimization. However, as the chip density keeps growing, it becomes challenging to find speed-paths of one chip from all sensitized paths with at-speed scan test patterns.
In this work, we use the method in [1] to generate an initial speed-path candidate (or suspect) set which has been proved to contain all real speed-paths. At first we derive a methodology to find conclusive speed-path by observing the relationship between the speed-path suspects. Then for the other speed-paths suspects called inconclusive speed-paths, we use a novel Boolean expression algorithm to provide a solution set for all possible combinations that describe the observed failing bits. By dealing with these Boolean expressions, we can remove fake speed-paths that cannot result in errors on the output. Finally we can feedback the conclusive speed-path and the remaining speed-paths to debug engineer to do design fix and performance optimization. | en |
dc.description.provenance | Made available in DSpace on 2021-06-07T17:53:19Z (GMT). No. of bitstreams: 1 ntu-101-R99943097-1.pdf: 8379733 bytes, checksum: 49b0f3b744a9bdcabdc66b491bff0048 (MD5) Previous issue date: 2012 | en |
dc.description.tableofcontents | 口試委員會審定書 i
誌謝 ii 中文摘要 iii Abstract iv Table of Contents v List of Figures vi List of Tables vii Chapter 1 Introduction 8 Chapter 2 Related Work 12 2.1 Speed-path suspects identification 12 2.2 Speed-path identification 14 Chapter 3 Proposed Speed-path Selection Technique 18 3.1. Introduction 18 3.2. Conclusive paths and inconclusive paths 19 3.2.1. Path definition 19 3.2.2. Conclusive path 20 3.2.3. Inconclusive path 21 3.3. Proposed algorithm to find conclusive speed-path 22 3.3.1. Algorithm and proof 22 3.3.2. Discussion 27 3.4. Boolean expression methodology 29 3.4.1. Boolean expression algorithm and implementation 30 3.4.2. Boolean expression examples and re-convergence cases 34 3.4.3. Dynamic hazard issue 39 3.5. Fake path removal 41 Chapter 4 Experimental Results 43 4.1. Experimental setup 43 4.2. Pattern set and circuit under test 46 4.3. Experimental results with proposed criteria 46 4.4. Discussion 49 Chapter 5 Conclusion 51 Bibliography 52 | |
dc.language.iso | zh-TW | |
dc.title | 在速掃描鏈測試中速度路徑診斷之改良 | zh_TW |
dc.title | Improving Speed-Path Diagnosis Resolution for At-Speed Scan Testing | en |
dc.type | Thesis | |
dc.date.schoolyear | 100-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 李建模(Chien-Mo Li),陳竹一(Jwu-E Chen),溫宏斌(Hung-Pin Wen) | |
dc.subject.keyword | 在速測試,速度路徑,診斷, | zh_TW |
dc.subject.keyword | Speed Path,Diagnosis,At-Speed Scan Testing, | en |
dc.relation.page | 54 | |
dc.rights.note | 未授權 | |
dc.date.accepted | 2012-08-18 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
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ntu-101-1.pdf 目前未授權公開取用 | 8.18 MB | Adobe PDF |
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