於邏輯掃描測試培養中除錯及預防異常高的最小工作電壓

Abstract

在行動晶片的品質驗證中，at-speed 邏輯掃描測試是一項重要工具。在初期測試樣本導入階段，若測試展現出異常偏高的 Vmin，可能導致過度測試，進而影響量產良率，這種情況尤其在測試的 Vmin 顯著高於實際系統工作負載的 Vmin 時更為嚴重，在這類情況下，工程師會對 at-speed 邏輯掃描測試進行除錯，以找出並解決造成高 Vmin 的根本原因。本論文介紹一個 Vmin 除錯的案例研究，透過一系列實驗，找出問題根源為某些測試樣本擷取了未受約束路徑的響應。我們提出了晶片前期（pre-silicon）與後期（post-silicon）的方法，藉由預防問題樣本並減少測試導入期間的除錯負擔，以改善 Vmin，這些方法已在 ATE（自動測試設備）上驗證，能有效改善 Vmin，提升幅度為 28.83mV 至 39.33mV，且測試向量僅增加0% 至 0.5%。

At-speed logic scan tests are an important tool to ensure desired quality in mobile chips. During initial test pattern bring-up, tests that exhibit an unexpectedly high Vmin pose a risk of over-testing and production yield loss. This is particularly problematic if the Vmin of the test is significantly higher than that of the functional system workloads. In such situations, the at-speed logic scan test is debugged to find and resolve the source of the high Vmin. This thesis describes an example case study of Vmin debug, in which a series of experiments are performed to identify the root cause as individual test patterns that capture the responses of unconstrained paths. We propose pre-silicon and post-silicon methods to improve Vmin by preventing problematic patterns and reducing the debug effort during test bring-up. Our methods have been verified on ATE to effectively improve Vmin by 28.83mV to 39.33mV with 0% to 0.5% pattern count inflation.