使用電壓控制幅度解碼器實現具頻率偵測器之四階脈衝振幅調變鲍率接收器

Abstract

本論文主要分為兩個部分。第一部分介紹具一個決策反饋均衡器每秒六百四十億位元的四階脈衝振幅調變鮑率接收機。 利用我們提出的電壓控制幅度解碼器以及鮑率相位偵測技術以減少比較器數量， 此四分之一速率接收機使用四個比較器、八個電壓控制幅度解碼器及積分器進行數據取樣，並且在不增加硬體數量之下能有頻率偵測器的功能。 其中比較器的偏移電壓進行前景式校正。 此接收機使用 28 奈米 CMOS 製程製造， 面積為 0.109 平方毫米。 在 15.3dB 的通道損耗之下達到位元錯誤率小於 10-12。 此接收機的總功耗為 172.2 毫瓦，計算所得能量效率為 2.69 每位元皮焦耳。 第二部分介紹每秒八百億位元的四階脈衝振幅調變鮑率接收機。 利用電壓控制幅度解碼器與基於資料樣式的鮑率相位偵測技術， 進一步減少接收機所需電路， 提出一個四分之一速率接收機使用四個比較器、八個電壓控制幅度解碼器進行數據取樣，並且在同樣不增加硬體數量之下能有頻率偵測器的功能。 其中比較器的偏移電壓進行前景式校正， 電壓控制幅度解碼器則自適應調整。 此接收機使用 28 奈米 CMOS 製程製造，面積為 0.083 平方毫米。 在 9.5dB 的通道損耗之下達到位元錯誤率小於 10-12。 此接收機的總功耗為 64.5 毫瓦，計算所得能量效率為 0.81 每位元皮焦耳。

This thesis is mainly divided into two parts. The first part presents a 64-Gb/s baudrate receiver for four-level pulse amplitude modulation (PAM-4), incorporating a one-tap decision-feedback equalizer. By using the proposed voltage-controlled magnitude decoder (VCMD) and a baud-rate phase detection technique, the required comparator count is reduced. The quarter-rate receiver uses four comparators, eight VCMDs, and integrators for data sampling, and supports frequency detection without additional hardware. Foreground calibration is applied to correct the offset voltage of the comparator. The receiver is fabricated by a 28-nm CMOS process, and its area is 0.109 mm². With a channel loss of 15.3 dB, the measured bit error rate is lower than 10−12. The total power consumption is 172.2 mW, corresponding to an energy efficiency of 2.69 pJ/bit. The second part presents an 80-Gb/s PAM-4 baud-rate receiver. By using the VCMD and a pattern-based baud-rate phase detection technique, we further simplify the receiver. The quarter-rate design using four comparators and eight VCMDs is proposed for data sampling, while frequency detection is also achieved without increasing hardware complexity. Foreground calibration is applied to correct the offset voltage of the comparator, and the control voltage of the VCMD is adaptively adjusted. The receiver is fabricated by a 28-nm CMOS process, and its area is 0.083 mm². With a 9.5 dB channel loss, the measured bit error rate is lower than 10−12. The total power consumption is 64.5 mW, corresponding to an energy efficiency of 0.81 pJ/bit.