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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/99727完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 劉深淵 | zh_TW |
| dc.contributor.advisor | Shen-Iuan Liu | en |
| dc.contributor.author | 翁丞甫 | zh_TW |
| dc.contributor.author | Cheng-Fu Weng | en |
| dc.date.accessioned | 2025-09-17T16:30:01Z | - |
| dc.date.available | 2025-09-18 | - |
| dc.date.copyright | 2025-09-17 | - |
| dc.date.issued | 2025 | - |
| dc.date.submitted | 2025-08-06 | - |
| dc.identifier.citation | [1] L. Feng, T. Li, X. Zou, X. Xiong, and Z. Zhang, “A 6–64-Gb/s 0.41-pJ/Bit Reference-Less PAM4 CDR Using a Frequency-Detection-Gain-Enhanced PFD Achieving 19.8-Gb/s/μs Acquisition Speed,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 72, no. 1, pp. 68-72, Jan. 2025.
[2] Z. Zhang et al., “A 64-Gb/s Reference-Less PAM4 CDR with Asymmetrical Linear Phase Detector Soring 231.5-fsrms Clock Jitter and 0.21-pJ/bit Energy Efficiency in 40-nm CMOS,” Proc. IEEE Symp. VLSI Technol. Circuits, June 2023, pp. 1–2. [3] S. Roh, K. Lee, M. Shim, M. -C. Choi and D. -K. Jeong, "A 64-Gb/s PAM-4 Receiver with Transition-Weighted Phase Detector," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 69, no. 9, pp. 3704-3708, Sept. 2022. [4] A. Cevrero et al., “A 100 Gb/s 1.1 pJ/b PAM-4 RX with Dual-Mode 1-Tap PAM-4/3-Tap NRZ Speculative DFE in 14 nm CMOS FinFET,” IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2019, pp. 112–114. [5] H. Li, C.-M. Hsu, J. Sharma, J. Jaussi, and G. Balamurugan, “A 100-Gb/s PAM-4 Optical Receiver with 2-tap FFE and 2-tap Direct-Feedback DFE in 28-nm CMOS,” IEEE J. Solid-State Circuits, vol. 57, no. 1, pp. 44–53, Jan. 2022. [6] J. Sim, C. Sim, J. Choi, S. Park, S. Kim and C. Kim, "A 50 Gb/s PAM-4 Transceiver with High-Swing Driver, Dual-Loop Analog Equalizer, and Integrator-Based Baud-Rate Linear CDR for Short-Reach Links," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 72, no. 4, pp. 1598-1608, April 2025. [7] N. Qi et al., “A 51 Gb/s, 320 mW, PAM4 CDR with Baud-Rate Sampling for High-Speed Optical Interconnects,” Proc. IEEE Asian Solid-State Circuits Conf. (A-SSCC), Nov. 2017, pp. 89–92. [8] H. Park, J. Sim, Y. Choi, J. Choi, Y. Kwon, and C. Kim, “A 56-Gb/s PAM-4 Receiver Using Time-Based LSB Decoder and S/H Technique for Robustness to Comparator Voltage Variations,” IEEE J. Solid-State Circuits, vol. 57, no. 2, pp. 562–572, Feb. 2022. [9] S. Park et al., "A 0.83pJ/b 52Gb/s PAM-4 Baud-Rate CDR with Pattern-Based Phase Detector for Short-Reach Applications," IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2023, pp. 118–120. [10] Y. -P. Huang and S. -I. Liu, "A 48-Gb/s Baud-Rate PAM-4 Receiver Using Modified Time-Interpolated Latches," IEEE Trans. Circuits Syst. II, Exp.62 Briefs, vol. 71, no. 9, pp. 4156-4160, Sept. 2024. [11] X. Zhao, Y. Chen, L. Wang, P. -I. Mak, F. Maloberti and R. P. Martins, “A Sub-0.25-pJ/bit 47.6-to-58.8-Gb/s Reference-Less FD-Less Single-Loop PAM-4 Bang-Bang CDR with a Deliberate-Current-Mismatch Frequency Acquisition Technique in 28-nm CMOS,” IEEE J. Solid-State Circuits, vol. 57, no. 5, pp. 1358-1371, May 2022. [12] P. -Y. Chou, W. -M. Chen and S. -I. Liu, "A 16-Gb/s Baud-Rate CDR Circuit with One-Tap Speculative DFE and Wide Frequency Capture Range," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 32, no. 3, pp. 480-484, March 2024. [13] V. Stojanovic et al., “Autonomous Dual-Mode (PAM2/4) Serial Link Transceiver with Adaptive Equalization and Data Recovery,” IEEE J. SolidState Circuits, vol. 40, no. 4, pp. 1012-1026, April 2005. [14] Y. -H. Lan and S. -I. Liu, "A 0.079-pJ/b/dB 32-Gb/s 2× Half-Baud-Rate CDR Circuit with Frequency Detector," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 32, no. 4, pp. 704-713, April 2024. [15] D. Kim, W. -S. Choi, A. Elkholy, J. Kenney and P. K. Hanumolu, "A 15-Gb/s Sub-Baud-Rate Digital CDR," IEEE J. Solid-State Circuits, vol. 54, no. 3, pp. 685-695, March 2019. [16] Z. Wang, Y. Zhang, Y. Onizuka, and P. R. Kinget, “Multi-Phase Clock Generation for Phase Interpolation with A Multi-Phase, Injection-Locked Ring Oscillator and A Quadrature DLL,” IEEE J. Solid-State Circuits, vol. 57, no. 6, pp. 1776–1787, June 2022. [17] B. Razavi, “The StrongARM Latch,” IEEE Solid-State Circuits Mag., vol. 7, no. 2, pp. 12–17, June 2015. [18] E. Depaoli et al., “A 64 Gb/s Low-Power Transceiver for Short-Reach PAM-4 Electrical Links in 28-nm FDSOI CMOS,” IEEE J. Solid-State Circuits, vol. 54, no. 1, pp. 6–17, Jan. 2019. [19] J. -E. Lin and S. -I. Liu, " A 0.875–0.95-pJ/b 40-Gb/s PAM-3 Baud-Rate Receiver with One-Tap DFE," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 33, no. 1, pp. 168-178, Jan. 2025. [20] Y. -P. Lin, P. -J. Peng, C. -C. Lu, P. -T. Shen, Y. -C. Jao and P. -H. Hsieh, "A 2.16pJ/b 112Gb/s PAM-4 Transceiver with Time-Interleaved 2b/3b ADCs and Unbalanced Baud-Rate CDR for XSR Applications in 28nm CMOS," IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig.Tech. Papers, Feb. 2024, pp. 136–138. | - |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/99727 | - |
| dc.description.abstract | 本論文主要分為兩個部分。第一部分介紹具一個決策反饋均衡器每秒六百四十億位元的四階脈衝振幅調變鮑率接收機。 利用我們提出的電壓控制幅度解碼器以及鮑率相位偵測技術以減少比較器數量， 此四分之一速率接收機使用四個比較器、八個電壓控制幅度解碼器及積分器進行數據取樣，並且在不增加硬體數量之下能有頻率偵測器的功能。 其中比較器的偏移電壓進行前景式校正。 此接收機使用 28 奈米 CMOS 製程製造， 面積為 0.109 平方毫米。 在 15.3dB 的通道損耗之下達到位元錯誤率小於 10-12。 此接收機的總功耗為 172.2 毫瓦，計算所得能量效率為 2.69 每位元皮焦耳。
第二部分介紹每秒八百億位元的四階脈衝振幅調變鮑率接收機。 利用電壓控制幅度解碼器與基於資料樣式的鮑率相位偵測技術， 進一步減少接收機所需電路， 提出一個四分之一速率接收機使用四個比較器、八個電壓控制幅度解碼器進行數據取樣，並且在同樣不增加硬體數量之下能有頻率偵測器的功能。 其中比較器的偏移電壓進行前景式校正， 電壓控制幅度解碼器則自適應調整。 此接收機使用 28 奈米 CMOS 製程製造，面積為 0.083 平方毫米。 在 9.5dB 的通道損耗之下達到位元錯誤率小於 10-12。 此接收機的總功耗為 64.5 毫瓦，計算所得能量效率為 0.81 每位元皮焦耳。 | zh_TW |
| dc.description.abstract | This thesis is mainly divided into two parts. The first part presents a 64-Gb/s baudrate receiver for four-level pulse amplitude modulation (PAM-4), incorporating a one-tap decision-feedback equalizer. By using the proposed voltage-controlled magnitude decoder (VCMD) and a baud-rate phase detection technique, the required comparator count is reduced. The quarter-rate receiver uses four comparators, eight VCMDs, and integrators for data sampling, and supports frequency detection without additional hardware. Foreground calibration is applied to correct the offset voltage of the comparator. The receiver is fabricated by a 28-nm CMOS process, and its area is 0.109 mm². With a channel loss of 15.3 dB, the measured bit error rate is lower than 10−12. The total power consumption is 172.2 mW, corresponding to an energy efficiency of 2.69 pJ/bit.
The second part presents an 80-Gb/s PAM-4 baud-rate receiver. By using the VCMD and a pattern-based baud-rate phase detection technique, we further simplify the receiver. The quarter-rate design using four comparators and eight VCMDs is proposed for data sampling, while frequency detection is also achieved without increasing hardware complexity. Foreground calibration is applied to correct the offset voltage of the comparator, and the control voltage of the VCMD is adaptively adjusted. The receiver is fabricated by a 28-nm CMOS process, and its area is 0.083 mm². With a 9.5 dB channel loss, the measured bit error rate is lower than 10−12. The total power consumption is 64.5 mW, corresponding to an energy efficiency of 0.81 pJ/bit. | en |
| dc.description.provenance | Submitted by admin ntu (admin@lib.ntu.edu.tw) on 2025-09-17T16:30:01Z No. of bitstreams: 0 | en |
| dc.description.provenance | Made available in DSpace on 2025-09-17T16:30:01Z (GMT). No. of bitstreams: 0 | en |
| dc.description.tableofcontents | 摘要....................................................................................................................i
Abstract.............................................................................................................iii Contents.............................................................................................................v List of Figures...................................................................................................vii List of Tables.....................................................................................................xi 1. Introduction.........................................................................................1 1.1 Motivation.................................................................................1 1.2 PAM-4 Signaling....................................................................... 2 1.3 Wireline Receiver......................................................................3 1.4 CDR.......................................................................................... 4 1.5 Thesis Organization...................................................................5 2. A 64-Gb/s Baud-Rate PAM-4 Receiver Using Voltage-Controlled Magnitude Decoder with One-Tap DFE and Frequency Detector...6 2.1 Motivation..................................................................................6 2.2 Circuit Description.....................................................................8 2.2.1 Time-domain decoder using the proposed VCMD.........8 2.2.2 DLEV Tracking Circuit..................................................12 2.2.3 Phase and Frequency Acquisition...................................13 2.2.4 Proposed Quarter-rate PAM-4 Receiver.........................16 2.3 Simulated Result........................................................................19 2.4 Experimental Result...................................................................24 3. An 80-Gb/s Baud-Rate PAM-4 Receiver Using Adaptive Voltage-Controlled Magnitude Decoder with Frequency Detector................31 3.1 Motivation.................................................................................31 3.2 Circuit Description.....................................................................33 3.2.1 PAM-4 RX using VCMD...............................................33 3.2.2 Phase and Frequency Acquisition..................................38 3.2.3 Data Level and Reference Adaptation............................41 3.2.4 Proposed Quarter-rate PAM-4 Receiver.........................44 3.3 Simulated Result........................................................................47 3.4 Experimental Result...................................................................49 4. Conclusion and Future Work..............................................................59 4.1 Conclusion..................................................................................59 4.2 Future Work................................................................................60 Bibliography......................................................................................................61 | - |
| dc.language.iso | en | - |
| dc.subject | 四階脈衝振幅調變 | zh_TW |
| dc.subject | 接收機 | zh_TW |
| dc.subject | 電壓控制幅度解碼器 | zh_TW |
| dc.subject | 鮑率 | zh_TW |
| dc.subject | 頻率偵測器 | zh_TW |
| dc.subject | 相位偵測器 | zh_TW |
| dc.subject | 時脈與資料恢復 | zh_TW |
| dc.subject | Receiver | en |
| dc.subject | Clock and data recovery | en |
| dc.subject | Phase detector | en |
| dc.subject | Frequency detector | en |
| dc.subject | Baud-rate | en |
| dc.subject | Voltage-controlled magnitude decoder | en |
| dc.subject | Four-level pulse amplitude modulation | en |
| dc.title | 使用電壓控制幅度解碼器實現具頻率偵測器之四階脈衝振幅調變鲍率接收器 | zh_TW |
| dc.title | A 64-Gb/s and An 80-Gb/s Baud-Rate PAM-4 Receiver Using Voltage-Controlled Magnitude Decoder with Frequency Detector | en |
| dc.type | Thesis | - |
| dc.date.schoolyear | 113-2 | - |
| dc.description.degree | 碩士 | - |
| dc.contributor.oralexamcommittee | 楊清淵;林宗賢;李泰成;薛育理 | zh_TW |
| dc.contributor.oralexamcommittee | Ching-Yuan Yang;Tsung-Hsien Lin;Tai-Cheng Lee;Yu-Li Hsueh | en |
| dc.subject.keyword | 四階脈衝振幅調變,接收機,電壓控制幅度解碼器,鮑率,頻率偵測器,相位偵測器,時脈與資料恢復, | zh_TW |
| dc.subject.keyword | Four-level pulse amplitude modulation,Receiver,Voltage-controlled magnitude decoder,Baud-rate,Frequency detector,Phase detector,Clock and data recovery, | en |
| dc.relation.page | 62 | - |
| dc.identifier.doi | 10.6342/NTU202503424 | - |
| dc.rights.note | 未授權 | - |
| dc.date.accepted | 2025-08-09 | - |
| dc.contributor.author-college | 電機資訊學院 | - |
| dc.contributor.author-dept | 電子工程學研究所 | - |
| dc.date.embargo-lift | N/A | - |
| 顯示於系所單位： | 電子工程學研究所 | |
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