應用於3D異質介質穩態熱分析之雙層級域分解方法

Abstract

現代三維積體電路 (3-D IC) 因垂直堆疊與高功率密度，帶來前所未有的熱管理挑戰。為突破單一全域有限元素分析在百萬級網格上動輒耗盡記憶體的瓶頸，本論文提出一種雙層級域分解方法，實現複雜三維異質介質結構的記憶體高效穩態熱分析。 所提方法將熱分析全域依分層結構劃分為垂直子域，獨立求解各子域同時透過迭代強制介面上的溫度與熱通量連續性。關鍵創新為雙階段求解過程，首先，預求解粗網格全域問題以較少計算資源捕捉整體溫度分布，接著細網格子域問題使用粗解作為初始邊界條件來精修局部熱場。此階層式策略將典型迭代次數從超過50次降至約15-20次。 模擬結果顯示，與傳統有限元素分析相比，記憶體消耗降低71-78%，同時維持節點溫度誤差在0.25%內。此外，框架的模組化設計允許以替代求解器取代有限元素核心，創造與其他工具或神經網路求解器整合的彈性，以進一步提升整體效能。本研究為先進封裝技術的熱分析提供一條實用的途徑，透過將記憶體受限問題轉換為可實行的計算流程，此方法實現異質整合時代中可靠度導向設計所需的前期熱分析架構。

Modern three-dimensional integrated circuits present unprecedented thermal management challenges due to their vertical integration and increased power densities. This thesis develops a two-level domain decomposition method that enables memory-efficient steady-state thermal analysis of complex 3D heterogeneous structures representative of integrated circuit packages. The approach addresses the fundamental limitation of conventional finite element methods, which require prohibitive memory resources when applied to detailed package models containing millions of elements. The proposed method partitions the thermal domain into vertical subdomains, solving each subdomain independently while iteratively enforcing temperature and flux continuity at interfaces. An innovation is the two-stage solution process, first, a coarse global problem captures the overall temperature distribution using lower computational resources; subsequently, fine-mesh subdomain problems refine local thermal fields using the coarse solution as initial boundary conditions. This hierarchical strategy reduces the typical iteration count from over 50 to approximately 15-20 cycles. Three benchmark cases validate the approach. Across all cases, memory consumption decreases by 71-78% compared to traditional FEM solvers while maintaining temperature accuracy within 0.25%. The framework's modular design allows substitution of the finite element kernel with alternative solvers, creating opportunities for integration with commercial tools or emerging physics-informed neural networks. This work provides a practical pathway for thermal sign-off of advanced packaging technologies. By transforming memory-limited problems into computationally tractable analyses, the method enables early-stage thermal exploration essential for reliability-aware design in the era of heterogeneous integration.